SHASHIDHAR T.

Email ID: acf29v@r.postjobfree.com

Mobile: +91-990*******

CAREER OBJECTIVE

Career as Full Custom Design Engineer that gives me an opportunity to utilize my skills and abilities in

Semiconductor Industry which offers professional growth.

TECHNICAL SUMMARY

Completed Masters(MS) in VLSI System Design from Coventry University U K

Completed BE in Electronics and Communication domain from Visvesvaraya Technological

University

Presented an Technical paper on "Implementation of the Dadda's Multiplier on ASIC Flow" at

international conference on VLSI 2013,Bangalore Sponsored by IEEE

Presented an journal on "Implementation of Block Error Correction coding techniques" at

International conference on VLSI and signal processing held on 4th May 2012,Bangalore

Presented an Technical paper on "3G Robo and its survivallence" at International conference on

Emerging Technology trends in Advanced Engineering Research held on 20th Feb 2012,Kerala

Presented an Technical Paper on "Reverse Engineering of Malware on Android" at National Level

Technical Student Paper Presentation held on 14th October 2011

SKILL SETS

Hardware Languages : Verilog and SystemVerilog

Software Languages : C and assembly language

EDA Tools Experience :

o Full Custom tools: Cadence:

o Virtuoso 6.1

o Calibre ( DRC, LVS, PEX, Compatibility check, ERC)

o Physical Design Tools: Synopsys - IC Compiler

o Spice Level Simulation: Spectre

Mentor Graphics – ELDO, LT Spice

o

o Scripting Language: TCL

o RTL Design & Verification: Verilog HDL

o QuestaSim, Model Sim, Xilinx ISE

o RTL Synthesis: Synopsys - Design Complier (DC)

o Timing Analysis (STA): Synopsys - Prime Time Suite (PT)

o PCB Design: OrCAD Capture, Layout Plus, Layout Translator, Allegro PCB SI

CORE COMPETENCY

Proficient in Full Custom IC Design (40nm, 65nm, 90nm, 130nm & 180nm)

Good Understanding of IO, Memories & Analog Chip Development

Full Custom top level Chip Integration.

Complete knowledge of ASIC flow (RTL to GDS)

Circuit Design & Layout Design.

Good knowledge of ESD and IC Fabrication process

Proficient in design and verification using Verilog and System Verilog

Proficiency in RTL coding, state machine design and test bench development

Experience in Physical Design (Floor Planning, Placement, Clock Tree Synthesis,

Routing, Physical Verification, DFM) at the block level and chip level

Proficiency in Static Timing Analysis

Hands on experience with P&R, DRC, LVS, PEX and standard cell layout designing

EDUCATIONAL BACKGROUND

M.S [Engg.] in VLSI system design (70% ), [Sept 2012 - July 2014]

M.S.Ramaiah School of Advanced Studies [Coventry University, UK], Bangalore

Bachelors of Engineering [B.E.] in Electronics and Communication (58%), [2012]

GSS Institute of Technology [VTU, Belgaum], Bangalore

PCMC, Higher Education

VET College [PUC], Bangalore

BHS School, Bangalore, Secondary Education

PROJECTS UNDER TAKEN

Title Integrated Circuit Analysis and Design

Developed and designed an Decoder for Memory cell with 6 bit address lines

My Role

and the 64 bit word lines

Issues faced Glitches in the output were found. Hence in order to avoid these glitches an low

power technique such as Glitch Reduction technique was used

& resolved

Cadence Virtuoso Layout Design

Tools used

Title Full Custom Physical Design

Designed and Developed an low power Full adder circuit and Layout

My Role

Cadence Virtuoso Layout Design & Assura for Verification.

Tools used

Analog and Mixed Signal Circuit Design

Title

Design of the 4 bit flash ADC and Static and Dynamic characteristics of ADC

My Role

was analyzed. Validation of the designed ADC was performed.

Hspui A,Cosmoscope

Tools used

RF Microelectronic System Development

Title

Power amplifier of the type NE651R479A was designed and developed which is

My Role

then integrated with a low pass filter. The low pass filter was designed using

lumped components.

Advanced Design System

Tools used

Title Design & verification of ATM controller using System Verilog

Modeling of controller using SV constructs, simulation using linear,

iterative, randomized test cases followed by inserting assertions to the

My Role

design & code coverage analysis

Considering all possible combinations/corner cases at the traffic

Issues faced

junction, maximizing code coverage

& resolved

VCS and Design Compiler from Synopsys

Tools used

Title Verification plan for ATM Controller

Develop state machine for the controller to initialize the ATM and to

perform various operations involved (bank and column selection, burst

My Role

read/write, precharge) & verification plan with the help of an Interactive Module

fnom lizicron memory and performing burst operations

Ir itia M ing the

Issues faced

& resolved

VCS and Design Compiler (Synopsys)

Tools used

Semi-custom design of Wallace tree, carry save adder, 128x8 memory

Title

RTL level code development, synthesis of all sub blocks followed by the

integration of the sub blocks which includes creation of top design file for IO

My Role

pads, full chip floor plan, placement, routing, physical verification & back

antegtattion the sub blocks was a challenge

I nno ra i ng

Issues faced

& resolved

Model Sim (Mentor Graphics), DC, PT & IC Compiler (Synopsys)

Tools used

MINI PROJECTS

1. Physical design of ORCA processor at the chip level & I2C at the block level (Net list to GDSII)

2. Standard cell design of all basic gates with different drive strengths (x2, x4, x8, x16, and x32)

3. PCB design (schematic, footprints, placement, routing, SI analysis, EMI and crosstalk analysis)

of Handy Board

MAIN PROJECT

Developed an NoC architecture which is integrated with Advanced Encryption Standard (AES)

algorithm. Maximum operating frequency of developed NoC architecture with modified arbiter

routing logic is obtained as 404MHz. The proposed arbiter routing logic requires 2.47ns for output

response which is faster than existing routing logic. It consumes 1.9mW of power which is more than

random arbiter logic (1.8mW). With a tradeoff between speed and power, NoC architecture with high

performance in terms of speed and hardware resource utilization has been developed using XY

algorithm with proposed modified arbiter logic. In this work, a modified routing logic has been

proposed and developed for NoC architecture to overcome drawbacks of XY algorithm. The modified

arbiter has the 3 states of operation such as input, grant and output states. It solves dead lock problem

by checking buffer status of input ports in each clock cycle and adjusts its input port dynamically

based on which the request and grant signals has been generated. Head of line blocking problem has

been solved by authorizing the input port for transferring data preferentially if the buffer port is full.

PERSONAL DETAILS

Name Shashidhar T

04 - January 1989

Date of birth

Gender Male

#65, 7th Main, Opposite to Canara Bank,Jayanagar 2nd Block, Bangalore-560011

Permanent

Address

Mobile +91-990*******

Email acf29v@r.postjobfree.com

Passport Number K7763223

Nationality Indian

Languages

English, Kannada, Hindi, Tamil,Telugu

Known

Hobbies Basketball, Watching movies, Referring IEEE Papers

SUMMARY

Exposure to EDA Design Tools from Synopsys, Cadence and Mentor Graphics

RTL Design using Verilog and System Verilog

Verification using Verilog and System Verilog

CMOS circuit design and Layout Design

Strong interpersonal skills

Believe in teamwork and smart work

A keen, quick learner

DECLARATION

I hereby declare that the above mentioned details are true to the best of my knowledge.

Place: Bangalore (Shashidhar T)

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