CURRICULUM VITAE

PERI ANURAG REDDY acf1wb@r.postjobfree.com

H-no : 5-164 Mobile:+918*********

Suraram colony, IDA jeedimetla

Hyderabad, 500055.

Career Objective

To be placed at a responsible position in a company where I can utilize my skills and knowledge

for the attainment of its goals and prove myself as a valuable asset to it. I would strive hard for the

growth of the organization, which in turn contributes to my personal growth.

Academic Profile

Course Discipline / School/College Year of pass %

Specialization

Advanced Diploma ASIC Frontend IIVDT Bangalore 2014 -

In VLSI Design Design

B.Tech ECE AURORA’S Scientific 2013 70.40

And Technological Inst,

Hyderabad.

Intermediate MPC Sir C.V Raman Jr. College, 2009 78.1

Wanaparthy

S.S.C. - Pragathi High School, 2007 77.1

Wanaparthy

Work Experience

• Working as Intern at Graphene Semiconductors, Bangalore. From July 2014 - present.

Technical skills

Programming Languages : Verilog HDL, System verilog HVL, VMM and UVM.

•

• Extra Languages : C Programing.

• Scripting Languages : Basic Shell Scripting.

Tools : Cadence NC Verilog, RTL compiler and Model Sim

•

Operating System : LINUX, Windows

•

Technical Subjects : Digital Design, CMOS Design.

•

Previous Projects & Experience :

Verification Of SPI Master Core Protocol using SV & UVM. July 2014-Aug 2014

• Verification Plan Creation.

• Design of Verification Environment.

• SPI Master DUT Analysis and Debugging.

• Functional Coverage analysis.

Design and Verification Of APB Slave Protocol using Verilog & SV. Mar-2014

• Design of APB Slave.

• Verification Plan Creation. & Design Of Verification Environment.

• APB Slave Verification Analysis and Debugging DUT.

Design of Sync & Async FIFO Verilog HDL. Feb-2014

• Design Plan Creation.

• Coding of Sync & Async FIFO Using Verilog HDL.

• Verification of DUT using Verification Environment.

Academic project :

Design of Cryptographic Processor using Verilog HDL Dec 2012-Feb 2013

• Design Plan Creation.

• Coding For Cryptographic 32-bit processor Using Verilog

• Debugging of Design.

Personal Profile

Name : Peri Anurag Reddy

Father's name : Peri Harshavardhan Reddy

Gender : Male

27th August, 1992

Date of Birth :

Languages known : Telugu, English and Hindi

Hobbies : Watching Cricket, Playing Cricket

Declaration

I hereby declare that the above information is true to the best of my knowledge and no misinterpretation is done.

Date:

Place: P ANURAG REDDY

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