S.BALAMURUGAN

Email: acf1mc@r.postjobfree.com

Mobile : +91-962*******

*/***-* ******* ***** Alagumuthunagar,Muthiyapuram Thoothukudi-628005

Objective

An enthusiastic and self-motivated experienced Physical design engineer looking for a

challenging and responsible position as Physical design engineer to apply my knowledge and

skill with my hard work and patience.

Working Experience

Organization : Arasan chip system, Thoothukudi-628008

Duration : November 2012 – August 2014 (1.9 years)

Designation : Design Engineer(Physical Design)

- Handle the tasks of performing physical design for CTS.

- Deep knowledge in floor plan, placement, CTS, routing and verification.

- Huge experience in timing optimization.

- Coordinated with layout and Design engineers, analyzed processes and implemented

necessary changes.

- Knowledge in soc encounter.

- Done lots of code in Perl.

- Having Strong troubleshooting qualities.

Academic Qualification

Bachelor Degree (B.E ) : Electronics and Communication Engineering.

University : Anna university 2008 -2012.

Institution : M.I.E.T Institution. Trichy.

Skills and Tools

- Scripts for fixing fanout violation, area calculation, buffer level detection.

- Scripts for pin ordering and automatic routing blockage.

- Floor plan for Integration of multiple blocks.

- Placement of std. cells using instance grouping.

- Buffer insertion on feed through paths.

- Manual modification over clock tree insertion from the tool.

- Slack elimination by up sizing, downsizing and inserting buffers.

- Buffer Insertion for critical paths.

- Fix setup/hold violations.

- Routing with optimization.

- DRC, LVS checks using Calibre.

*Synthesis : RC (Cadence).

*Design : Encounter (Cadence) .

*Physical Verification : Calibre (Mentor Graphics).

*Static Timing Analysis : ETS (cadence).

*Scripting Language : Perl.

PROJECT 5: Block level

Objective : Optimize for timing as well as for power.

Name : USB

Design size : 450 X 450 um

Technology : 180nm

Frequencies : 550 MHz

Role:

• Floor Plan, Power Plan, Placement.

• Timing Analysis, CTS, Detail Routing.

• DRC and LVS verification.

PROJECT 4: Physical Design & Verification

Objective : To do the floor planning, Power planning, placement, CTS.

Name : USB

Design size : 143 X 135 um

Technology : 40nm

Frequencies : 550 MHz

Role:

• Floor Plan, Power Plan, Placement .

• Timing Analysis, CTS, Detail Routing.

• Involved in good Floor Planning & Power Planning.

• DRC and LVS verification.

PROJECT 3: Physical Design & Verification

Objective : To do the floor planning, Power planning, placement, CTS.

Name : DPHY

Design size : 500 X 150 um

Technology : 55nm

Frequencies : 500MHz

Role:

• Floor Plan, Power Plan, Placement.

• Timing Analysis, CTS, Detail Routing.

• Involved in good Floor Planning & Power Planning.

• DRC and LVS verification.

PROJECT 2 : Physical Design & Verification

Objective : To do the floor planning, Power planning, placement, CTS.

Name : DPHY

Design size : 500 X 150 um

Technology : 65nm

Frequencies : 500MHz

Role:

• Floor Plan, Power Plan, Placement.

• Timing Analysis, CTS, Detail Routing.

• Involved in good Floor Planning & Power Planning.

• DRC and LVS verification.

PROJECT 1: Physical Design & Verification

Objective : To do the floor planning, Power planning, placement, CTS.

Name : DPHY

Design size : 250 X 200 um

Technology : 40nm

Frequencies : 750 MHz

Role:

• Floor Plan, Power Plan, Placement

• Timing Analysis, CTS, Detail Routing.

• Involved in good Floor Planning & Power Planning.

• DRC and LVS verification.

DECLARATION

I hereby declare that the above information is true to the best of my knowledge and belief.

Date: 2014 Signature

Place: Thoothukudi S.Balamurugan

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