nATIONAL iNSTITUTE OF tECHNOLOGY

TIRUCHIRAPPALLI

INDIA

SUMAN PACHIMATLA

MALE, INDIAN, 26

VINAYAKA PG, MARTHAHALLI,

BANGALORE,KARNATAKA-560037.

EMAIL: acf1kc@r.postjobfree.com

MOBILE NO: +919*********

CAREER OBJECTIVE

SEEKING A CHALLENGING POSITION IN THE ORGANIZATION THAT GIVES ME AN

OPPORTUNITY TO SHOW MY SKILLS AND IMPROVE MY KNOWLEDGE IN THE VLSI DOMAIN.

PROFILE SUMMARY

. EXCELLENT KNOWLEDGE AND ACADEMIC EXPERIENCE IN PHYSICAL DESIGN OF VLSI

CIRCUITS OBTAINED THROUGH RELATED COURSEWORK AND PROJECTS TO CREATE

LAYOUTS OF CMOS CIRCUITS.

. Having experience to Fix LVS & DRC issues for layout cells that had

edits in the schematics. Well versed with parasitic extraction,

LVS/DRC and other Physical verification checks.

. Having academic experience of digital design methodologies and tools

including RTL coding in Verilog, simulation and formal verification.

. Good knowledge of writing, simulating of Verilog code by using Quartus

II and Modelsim softwares.

. Excellent knowledge on VLSI, CMOS, Static Timing Analysis (STA) and

Finite State Machine (FSM).

. Understanding of Digital Electronics and academic experience in the

field of Digital Systems Design.

EDUCATION

. M-TECH IN VLSI SYSTEMS WITH 8.50 CGPA AT NATIONAL INSTITUTE OF

TECHNOLOGY, TIRUCHIRAPPALLI IN 2014

. B-TECH IN ELECTRONICS WITH 71.02% AT KAKATIYA INSTITUTE OF TECHNOLOGY

AND SCIENCE, WARANGAL, A.P.

. INTERMEDIATE WITH 94.10% AT SVS JUNIOR COLLEGE, HANAMKONDA, A.P.

. S.S.C. WITH 92.50% AT GOUTHAMI HIGH SCHOOL, JAMMIKUNTA, A.P.

PROJECT WORK / TRAINING

. Design of Low power, High speed Transceiver for on-chip serial

interconnects

The design of pseudo NMOS multiplexer circuit is discussed. Due to its

high power consumption and low speed, a new circuit "Domino

logic Multiplexer" that reduces the power consumption and increase the

speed of the operation is discussed. And a voltage mode receiver is

designed. Simulations are carried out in Cadence using UMC 180nm

technology.

. Design of Asynchronous FIFO with pointers synchronizing technique

using Verilog HDL

FIFOs are generally used to safely pass data from one clock domain to

another asynchronous clock domain. This design uses gray code pointers

that will be synchronized in to different clock domains before testing

FIFO full and empty conditions.

. Wireless Electromyograph

Electromyography is the study of electrical signals that the human

body generates when muscles contract. Surface electrodes are placed

directly on the skin overlying the muscle. EMG signals are small and

need to amplify by an amplifier, the filtered signal can be displayed

on an oscilloscope.

AREAS OF INTEREST

. Digital system design

. CMOS Logic design

. RTL Design

. Physical Design

SKILLS

Operating System : Windows XP/7,Linux

Languages : Verilog HDL, C

CAD Tools : Quartus II, Modelsim

Cadence (Assura-Virtuoso ADE(L),Spectre)

ACADEMIC ACHIEVEMENTS

. Won 2nd prize in school level talent search exam conducted by

ALPHORSE Academy

. Secured 435 Rank in GATE-2012

EXTRA CURRICULAR ACTIVITIES

. ORGANIZER FOR 'SANSKRITI', A CULTURAL FEST IN B.TECH.

. Coordinator for 'Parikaran'09', A National level Technical symposium

PERSONAL DETAILS

. FATHER'S NAME : MALLAIAH

. Date of Birth : 05th February 1988

. Linguistic Proficiency : English, Telugu &Hindi

I hereby declare that all the above information furnished is true and

correct.

Place: Signature

Date: Name: Suman Pachimatla

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