C u r r iculum Vitae

Sanghani

H a rdik

Phone :

+91-787*******

+91-932*******

E-M ail I d:

acf11e@r.postjobfree.com

m

acf11e@r.postjobfree.com.

in

Address:

D-2 Pavan park.

Behind Atmiya college,

Satya Sai Road,

Kalawad road.

Rajkot.

Gujarat- 360005

Languages Known:

E nglish, H indi, Gujarati

D ate of Bi rth

4th January 1990

Strength :

Hardworking

Fast learning

A bility to work in group

I nnovative

H obbies :

P laying Carom

L istening Music(rock, metal,

r ap)

Playing Badminton

Refrences :

Dr. Rahul Dubey (prof. DA-

I ICT)

Dr. Bhavin Sedani(HOD

V VP)

Objective

To excel and t ry to be best at whatever I do, To keep expanding the horizons of my

k nowledge, t ry doing newer and newer things and To be associated with a progressive

organization that provides an opportunity to apply my knowledge and skills while being

resourceful, innovative.

Education Qualification

(March 2013 –July 2014)

VLSI Design, Low power VLSI Design,

95 PERCENTILE

V LSI Subsystems Design,

Real Time Embedded Systems,

Low Power Digital Design, Timing

A nalysis.

C, C++, VHDL, Verilog HDL, Embedded

C

Cadence, Xilinx, MAT LAB, OrCAD, LT

Spice, ModelSim, LPCXpresso,

Codeblocks(GCC- compiler), AVR Studio,

Code Composer Studio (CCS), Silos,

Logisim

Low Power VLSI, VLSI Subsystem

Design, Digital System Architecture,

L abs in VLSI

Qualified Graduate

Aptitude test taken by

I IT’s four t imes

GATE-2011

GATE-2012 99 PERCENTILE

GATE-2013 98 PERCENTILE

GATE-2014 97 PERCENTILE

Academic Experience

Worked Two years as a Teaching Assistant in DA-I ICT

( June 2012- Ma rch 2014)

PROJECT

Design of custom w i reless protocol for signal

t ransmission inside satellite (M TEC H T H ES IS)

Guide : Dr. Rahul Dubey

Software Packages: (MATLAB, XIL INX, VERILOG)

There are large number of sensors and devices inside a satellite. All these devices need to communicate with

each other, they can be sensor nodes or control device. In the present day technology the communications of

t he different sensor nodes inside the satellite is wired which adds the weight of the harness cable. A wireless

p rotocol has been made and t ransceiver is being implemented in Verilog and implemented in Vixtex-5QV

FPGA.

Implementation of Processor Arithmetic using Verilog HDL (Sept. 2012 –Octo.2012)

Guide : Dr. Biswajit Mishra

Software Packages: (VERILOG)

Various subsystems of processor such as Adders, Multiplier, Divider, Pipelined ALU and Cordic Equations a re

i mplemented.

Design of a text message entry system using number keys, ATM machine (Nov.,2012 –Dec.,2012)

Guide : Dr. Biswajit Mishra

Software Packages: (VERILOG)

VHDL implementation of text message entry system using 0-9 keys and an ATM machine using Finite State

M achine (FSM).

Design of an low power Digital FIR filter (Jan.,2013 – March,2013)

Guide : Dr. Bhavin Sedani

Software Packages: (Cadence, Virtuoso)

Low power Digital FIR filter is designed using the optimized multiplier and adder, they are selected by doing

t he power analysis of various multipliers and adder prepared by various different methods using cadence

v irtuoso.

Multi featured Music Player with GUI (July 2010 – June. 2011)

Guide : Dr. Bhavin Sedani

Software Packages: (MATLAB)

Different effects like Karaoke, Surround Sound, Flanging, Reverb, Left/right Channel selection, Echo,

Chorus, Bass, and Treble are being simulated in MATLAB Simulink and implemented in TI DSK 6713.

Power analysis tool (March,2013 –Apri;2013)

Guide : Dr. Biswajit Mishra

Software Packages: (C, VERILOG, pearl)

Power drawn by any circuit depends on the number of zero to one (0 1) transitions made by output of any

logic gate. This information can be obtained from Value Change Dump (VCD) which is extracted so as to

calculate Dynamic power and static power for a given design and technology.

Optimal Supply and Threshold Scaling for Sub threshold CMOS (August,2013 –Oct.,2013)

Circuits

Guide : Dr. Biswajit Mishra

Software Packages: (LtSpice)

With technology scaling Power supply and threshold voltage continue to decrease, to satisfy high

performance and low power requirement sub-threshold CMOS circuits have been used in ultra-low power

circuit giving low to moderate performance (10kHz-100MHz). 180nm CMOS Circuit for the range of Vdd (0.1-

0.6) and Vth (0-0.6).We have been observed and analyzed, for the CMOS ring oscillator for various activity

factor. These results are useful in circuit designing which gives an insight into optimal threshold voltage and

supply voltage for a given application and specification.

Image compression using singular value decomposition (Octo.,2013 –Dec,2013)

Guide : Dr. Anjan Ghosh

Software Packages: (C,MATLAB)

T his project explores image compression by the use of singular value decomposition on image matrices

w here by image is divided into various sub blocks and dynamically depending on the image complexity the

n umber of elements required in S,V,D is determined and compression in done.

D EC LARAT IO N

T he information furnished above is correct and t rue to the best of my knowledge.

Yours Faithfully

Hardik Sanghani

Date: 15/09/2014

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