Objective

A Design and Verification Engineer position in an organization seeking

committed and fast learner with knowledge of Verilog, test benches &

verification techniques, along with hands-on experience on Synopsys tools.

Summary

I am working with Whizchip Design Technology since October 2011. I have

worked in SOC, VIP and IP Devolopment Projects.

Skills Summary

Syatem Verilog UVM/SVT/OVM Verilog HDL

Logic Design Perl RTL Design/Verification

Finite State Machine NCVERILOG AXI/AHB Protocal

Ethernet-10G Protocol ARC6.0 Processor GDDR5 Protocol

GPIO/UART/WDT Block UVM Component CDC/STA

Responsibilities Handled

Written Drriver, Monitor, Scoreboards,Sequence, Sequence Item, Testcase,

Interface, Debugging, Processor assembly programming level soc testing.

Netlist level debugging

Project Experience

Projects - Whizchip Design Tech

Ethernet 10g ip devolopment

o It's an IP development project which has XGMII interface . Our project

is divided into three blocks - MAC, MTL and EDMA. This IP also

supports SA/DA/VLAN Insertion/Replacement/VLAN Deletion, Double VLAN

Processing, Packet Filtering, PTP, ARP Offloading, Flow Control,

TCP/IP Checksum Offloading, TCP Segmentation Offloading, RSS Function,

OoS Function.

GDDR5 Vip devolopment

o It's a GDDR5 memory model development project. This project is

compatible with UVM/OVM/VMM/Verilog testbench environment.

SOLAR POWER CONSERVATION MIXED SIGNAL SOC DEVOLOPMENT

o It's a Mixed Signal SOC Devolopment Projects which is built on AHB and

APB bus. This is interfaced with the Analog Front end with the

ADC/DAC. This SOC contains the One Tine Fuse Memory and the Boot

Memory and also has an decription algorithm for data security.

Major Project - B.Tech Electronics & Telecommunication Engineering

8-bit processor IMPLEMENTATION(8085 Architecture)

o It's a RTL processor architecture and design project with the

reference of 8085.

International Paper

Speed and power optimization of 1-bit alu

o Modification of digital circuits in order to reduce the power and

speed from the standered digital design.

Education

Indian institute of vlsi design & Training -Bangalore, Karnataka

Advanced Diploma in VLSI Design & Technology, Sep 2011

Three Month Full Time Course in ASIC Design based on Cadence flow. Course

work included 150 hours of theory and 200 hours of lab work including

industry standard project work.

B.E in Electronics and Teleommunication Engineering, May 2011

Percentage: 68

NAGPUR UNIVERSITY, NAGPUR

Class XII DAV Public School, CBSE, 2007

Percentage: 66

Class X St. Joseph's High School, CBSE, 2005

Percentage: 72

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