RESUME

PIDUGU GOPI Cell: +**

949-***-****

E-mail:

acf0ap@r.postjobfree.com

Career Objective

To join a well-developed organization where I can apply my

functional and technical expertise, innovative thinking and hardworking

capability and contribute to the growth of the organization.

Professional Experience

Company : Cognos It Solutions. (March 2013 to present).

Role : Present working as VLSI Application Engineer,

Job description : writing codes by using both VERILOG and VHDL

and verify the code.

Place : Tarnaka. (Hyderabad).

Technical Skills

FPGA : Altera DE-2

Languages : C, Verilog HDL, VHDL

Development Tools : QuartusII-8.1, Xilinx ISE 13.3,Modelsim 10.0

Operating Systems : Windows XP/7

Packages : Microsoft Office

Academic

C-DAC's ADVANCED COMPUTING TRAINING SCHOOL Nagpur, MH, India

PG-Diploma in VLSI AND EMBEDDED 2013

70.85%

ADRSH COLLEGE OF ENGINEERING

Kakinada, AP, India

Bachelor of Engineering in ELECTRONICS AND COMMUNICATION 2008 - 2012

61.61%

NARAYANA JUNIOR COLLEGE

INTERMEDIATE

Visakhapatnam, AP, India

2006 - 2008

85.80%

Z.P.H SCHOOL

SSC

Munjeru, AP, India

2005-2006

75.16%

Extra-curricular Activities

. Participated in "ROBO ZEAL" in association with Li-2 Innovations,

Bangalore

. Secured second position in school in SSC

. Attended for 26th International Conference on VLSI Design and 12th

International Conference on Embedded Systems organised by IEEE.

Projects

Title Durati Platform Description

on In Used

Months

HUMMING BIRD 4 VHDL & Hummingbird is an ultra-lightweight

ALGORITHM Verilog encryption scheme and it has applications

HDL in privacy-preserving identification and

mutual authentication protocol for RFID

applications. Hummingbird is elegant

combination of 16-bit block size, 256-bit

key size. The size of the key provides

security level which is adequate for many

RFID applications. Hummingbird can provide

the designed security with a small block

size and is therefore expected to meet the

stringent response time and power

consumption requirements described in the

ISO protocol.

Asynchronous 1 VHDL & Asynchronous fifo is general purpose fifo

FIFO Verilog with configurable depth and data width. The

HDL fifo uses block RAM based storage by

default. The code is designed to be

technology independent. As a benchmark,

synthesis results have been provided for

Altera Cyclone II series of FPGA devices.

64-bit ALU 3 VHDL The main aim of this project will be to

using VHDL design a 64-bit ALU using VHDL module. It

module is used to perform 32 operations by using 2

opcodes.16 arithmetic operations through

opcode1 and 16 logical operations through

opcode2. Opcode will be selected by using a

multiplexer.

Personal Profile:

Date of Birth : 03rd March, 1990

Languages known : English, Telugu

Address : H.No: 3-75A,

Munjeru Village,

Bhogapuram Mandal,

Vizianagaram District,

AP, India

Declaration

I hereby declare that the above-mentioned information is correct up to my

knowledge and I bear the responsibility for the correctness of the

above-mentioned particulars.

Yours Sincerely

GOPI.P

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