SELVA GANESH ELANGOVAN

**, ********* **. ****, ****** Manor Rd, Toronto – M2J1M6, ON, Canada

E-mail: acezch@r.postjobfree.com Phone No: 437-***-****

SUMMARY OF QUALIFICATIONS

Experienced candidate as Junior Technical Staff member (FPGA Engineer) at MDA Satellite Systems

Recent Master’s graduate accountable for driving hardware design using VHDL, Verilog, System

Verilog and functional hardware verification using System Verilog, e, UVM

Proven expertise in designing and verifying MAC protocol for wireless body sensor networks

3 years of career related work experience across FPGA design and verification

Working knowledge of CAN and AMBA AXI 4 – Lite, AHB and APB protocols

Hands on experience with Oscilloscopes, Logic analyzers and Spectrum analyzers

Successful in defining test plans, test bench architecture, building UVM based test benches, debugging

and finding bugs in hardware

Ability to work on System Verilog, OVL Assertions and bring functional coverage closure

PROFESSIONAL EXPERIENCE

JUNIOR MEMBER OF TECHNICAL STAFF (FPGA ENGINEER, MDA Satellite Systems)

(Contract Nov 2013 – March 2014)

Responsible for developing bus functional models and monitors in Verilog for two FPGA designs

Design debugging and modification of RTL codes through various error injecting test-cases

Architected around 250 properties for the RTL design and converted it to OVL assertions (based on

System Verilog, Verilog and PSL libraries)

Work closely with the design team, to achieve reasonable code coverage and functional coverage

through assertions

Successfully completed verification of AMBA AHB (AHB master, slave, fabric, parallel bridge master

and slave modules), Clock-Reset, Automatic Identification System, Priority MUX and ANC modules

RESEARCH ASSISTANT (HARDWARE VERIFICATION GROUP, CONCORDIA UNIVERISTY)

Verification and Performance Analysis of TBCD protocol (Winter 2011- Winter 2013)

HARDWARE USED: Xilinx ML506, LINX OOK transceivers

SOFTWARE USED: Xilinx ISE, MATLAB and SIMULINK

Designed Synchronisation and clock drift error compensation method for a low power Implantable

Wireless Body Sensor (IWBSN) protocol named Time Based Coded Data (TBCD)

Proposed a verification framework for validating IWBSN protocols with in-body wireless channel,

modelled using SIMULINK according to IEEE 802.15.6 specifications

Verification framework enables to find optimum transmit power, sensitivity of the transceiver for

TBCD protocol to work efficiently for longer period of time inside the body

MAC layer along with the proposed methodologies were designed in RTL using VHDL and

demonstrated the working of protocol with a base station and three sensor nodes using Xilinx ML506

development kit

EDUCATION

Master of Applied Science (June 2013)

Concordia University, Montreal, QC, Canada

Electrical Engineering (Specialization: VLSI Design, Hardware Verification) GPA: 3.93

Relevant courses:

Digital Design and Synthesis, Formal Hardware Verification, ASIC Design, Optical Communication,

Microcontrollers for Mechatronics, Power Electronics, Functional hardware verification, Computer

Architecture, Digital Signal Processing (DSP)

Bachelor of Engineering: Electronics &Communication (2004-2008)

Anna University, Chennai, India. (First Class with Distinction)

ca.linkedin.com/in/esganesh/

CERTIFICATION COURSES

Functional hardware verification (Winter 2013)

Udacity, Cadence

Embedded System Programming (Summer, Fall 2007)

AUPERS-Anna University, Chennai, India

HARDWARE AND SOFTWARE PROFICIENCIES

Programming Languages: C, C++.

HDLs and HVLs: VHDL, Verilog, System Verilog for Design and Verification, e.

HV Methodology: UVM

IDE Tools: Xilinx ISE, Actel LIBERO, ModelSim, Cadence CMOSIS,

MATLAB/SIMULINK, Design Compiler (DC), Altera Quartus.

Verification tools: Cadence Conformal LEC, Synopsys Formality, Mentor QuestaSim.

Hardware: XILINX and ACTEL FPGAs, PIC18series, ARM cortex M0 series.

Scripting Languages: Perl

PUBLICATIONS

Elangovan, S.G.; Fereydouni-Forouzandeh, F.; Ait-Mohamed, O., "Performance analysis of TBCD

protocol over Wireless Body channel," IEEE 55th International Midwest Symposium on Circuits

and Systems (MWSCAS), 2012, vol., no., pp.1048,1051, 5-8 Aug. 2012

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6292203&isnumber=6291930

Elangovan, S.G.; Fereydouni-Forouzandeh, F.; Ait-Mohamed, O., "On Clock synchronization and

error compensation for TBCD protocol" (under review)

CAREER RELATED PROJECTS

Design and Implementation of mini-MIPS (System Verilog) (Fall 2012)

Starting from a paper-and-pencil design of the major blocks, a RISC pipelined processor, Mini-MIPS

was designed using System Verilog

Designed Data path and Control Unit including: fetch, decode, execute, memory, write back, data path

control

Wireless Control of Servomotors for Unmanned Ground Vehicle (Summer 2010)

Hardware: Xbee wireless module, BASYS2 Software: Xilinx ISE (RTL coding in VHDL), Adept2

Two servo motors of unmanned ground vehicle were controlled remotely

FPGA was used to send the control data to onboard Xbee

Asynchronous receiver and PWM generators were implemented in FPGA

Formal Verification of Direct Digital Synthesizer Design (DDS) (Summer 2010)

A synthesized buggy gate level description and a golden RTL level of the design was provided. The

RTL design was analyzed and synthesized using Synopsys Design Compiler

The errors introduced in the buggy gate design were found and fixed successfully using “Synopsys

Formality" and "Cadence Conformal Logical Equivalence Checker"

Design of PIC Microcontroller based Monitoring & Device Control System (C) (Winter 2010)

An embedded system design which fully controls the inside room temperature and light system of a

house was designed using PIC microcontroller

The project demonstrates the usage of major features of PIC18F microcontrollers. Based on the

sunlight intensity and the temperature sensed, the system will drive the cooler or the heater

Multiplier using Booth Algorithm (VHDL) (Fall 2009)

Developed a Pipelined Booth Multiplier and Accumulator (MAC) for two 8 bit binary numbers using

VHDL. Structural modelling was used and the design is extendable to 32 bits

Developed various test cases and was tested using simulation in ModelSim

Synthesis, Place and Route, Chip Planning on Actel ProASIC3 was done successfully

Feed Forward Neural Network Implementation using Layer Multiplexing (Verilog) (Summer 2008)

Low power FPGA implementation of multilayer feed forward neural networks using Xilinx Spartan5

Demonstrated reduced resource requirement using sequential processing and FPGA for a large neural

networks

ca.linkedin.com/in/esganesh/

Implementation of CAN protocol using LPC microcontrollers (Embedded C) (Summer, Fall 2007)

Implemented CAN protocol in LPC embedded kit to reduce the cost and space of mesh wiring and to

effectively connect the utility parts of the vehicle

LPC 2378, an ARM7TDMI-S based high performance 32-bit RISC processor was used and Embedded

C was used for programming the micro-controller

VERIFICATION EXPERIENCE

Functional hardware verification (Winter 2013)

Udacity, Cadence

Verification of Router (e and UVM)

A Verification environment for router was built step by step, incrementally. Initially, data to generate

different kinds of packets for the DUT was modeled

Developed infrastructure such as data automation, physical fields, interface ports, error handling and

strategies to check data movement on the DUT and its behaviour on the interfaces

Built test phases to synchronise and schedule different units of the test bench. Usage of features of e

like events, call-backs, ports, units, signal maps

Devised coverage plan for the DUT and implemented monitors to check the correctness of packet and

collect coverage at the right time. Modified the test environment with Aspect oriented programming

(AOP) and applied patches to the tests

Finally, converted the test environment in terms of UVM methodology using Universal Verification

Components (UVCs), agents etc. for reusing

Verification of 16650a UART with APB interface (System Verilog and UVM) (Summer 2013)

Developed block level functional coverage verification environment for industry standard 16650a

UART module with System Verilog and UVM methodology

Prepared a list of all the features to be tested and built the functional coverage model for different

blocks of the design

Incremental building of different phases such as agents, sequencers, registers models, test environment

etc.

Verification of Calculator (System Verilog) (Winter 2013)

Developed automated verification environment for two RTL designs of calculator with different

difficulty level using the features of System Verilog

Started from understanding the specification of calculator designs. Developed a deterministic

verification plan to build the test environment around the RTL design

Architected the test with environment, reset, data-model generation, driver, receiver, scoreboard,

coverage phases. Used features of System Verilog such as virtual interface, mailboxes, constrained

random verification etc

Found eleven bugs in the two calculator designs and fixed the fixable errors in the RTL design

CAREER RELATED EXPERIENCE

Research Assistant (Hardware Verification Group, Concordia University) (January 2010 – May2013)

Teaching Assistant & Lab Demonstrator (Concordia University) (January 2010– Fall 2012)

“Wireless Power Tariff Using Micro controller” in ASOFT Solutions (Summer 2006)

ACHEIVEMENTS

Recipient of Concordia Partial tuition fee scholarship for two semesters (Fall 2010 - Winter 2011)

Semi-finalist in “Lattice PLD/FPGA Design Challenge 2011” for the design titled "An inexpensive

electronic gadget for urban farmers in developed countries" (Fall 2011)

Implementation project titled “FPGA implementation of TBCD protocol” was selected for TEXPO

2011, Ottawa, Canada (Fall 2011)

ca.linkedin.com/in/esganesh/

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