DHIRAJ RAMESH GAWHANE

A-***, Krishna Complex, Sector 15,

Plot No.7, Palm Beach Road,

Sanpada, Navi Mumbai-400705. +91-987*******

Current Location – Bangalore, Karnataka : acex80@r.postjobfree.com; +91-886*******

CAREER OBJECTIVE

Seek a position in growing organization that provides the opportunity to make a strong

contribution to organizational goals through continued development of professional skills.

EDUCATIONAL QUALIFICATIONS

Course M.Tech B.E. H.S.C

Branch VLSI Design Electronics & Science

(Electronics) Telecommunication

Institution Visvesvaraya Vidyalankar Ramnivas Ruia

National Institute Institute Of Junior College

Of Technology, Technology.

Nagpur. (Mumbai

University).

Year of Passing 201*-****-****

Percentage/CGP 9.92 (max : 10) 77.06 % 79.5 %

A

Current position

• Project Intern (IC Team) at Saankhya Labs Pvt Ltd.

IC Team comprises of Design and Verification methodology sections. Currently, working under a

project which involves FrontEnd design and verification of modules.

PUBLICATIONS

Design and Implementation of Neighborhood Processing

a)

Operations on FPGA using Verilog HDL.

Publisher: IOSR journal of VLSI and Signal Processing (IOSRJVSP), [Volume 4,

Issue 1].

Design and Implementation of a Digital Image Processor for

b)

Image Enhancement Techniques using Verilog Hardware Description Language.

Publisher: International Journal of Computer Technology & Applications, [Volume 5,

Issue 1].

FPGA Implementation of SPI to I2C Bridge.

c)

Publisher: International Journal of Engineering Research & Technology, [Volume 2,

Issue 11].

VACATION TRAINING

• TATA Power, Trombay, Mumbai (12th July 2010 to 22nd July 2010).

Studied Unified SCADA system, Communication network and system, Distribution

automation system, Protection system and plant information system, Site visit to

500MW unit, Fibre optic joining and splicing.

TECHNICAL PROJECTS AND ACTIVITIES

• Modeling and Simulation of Fowler - Nordheim Program/Erase process in High-k

IPD Flash Memories. (June 2013 to

May 2014).

In this project, the quantum mechanical simulations of the flash memory structure by

writing mathematical models were performed. FEM and numerical methods were used

for the simulation purpose. Main aim of this work was to obtain the programming and

erasing characteristics in flash memory device by numerical simulations.

• Fabrication and Characterization of MOS capacitors (May-

June 2014).

In this activity, the fabrication was done at CEN, IIT-B under INUP. The MOS

capacitors were fabricated in class 100 fabrication laboratory. The instrument used for

the characterization (IV & CV) is 4200-SCS Parameter Analyzer from KEITHLEY.

• Design and Optimization of 65nm NMOS Device

(June 2013).

For this short term project, Design and optimization of all the process parameters was

performed according ITRS Norms to perform the simulation of 65 nm NMOS Process.

This was done in various packages given by Sentaurus TCAD (Synopsys).

• ASIC implementation of 16 bit Booth Multiplier (January 2014 to February

2014).

In this activity, I performed complete RTL to GDS II flow for the 16 bit booth multiplier.

For this, RTL level design was written in VHDL. Simulation was performed with 95%

code coverage to check its functionality in ModelSim (Mentor Graphics). Synthesis

was done in Design Compiler (Synopsys). Formal Verification was performed in

Formality (Synopsys). Final chip layout of RTL Design was created using SoC

Encounter (Cadence).

• Smart Antenna (July 2011 to April

2012).

A Smart Antenna is a device which uses the adaptive signal processing for efficient

use of power and minimizing the interferences. The technology can be used in many

applications like cellular phones. The design is simulated on the MATLAB Simulink by

making its test bench. The algorithm used for this was LMS and the BER of 0.001 was

obtained by simulations.

• Digital Clock (October

2012).

In this short term project entire structural level VHDL code was written for the digital

clock. The entire code was written and synthesized in the tool Xilinx ISE. The

correctness of the code was verified through simulation and also by dumping the code

in the FPGA (Virtex-II). The power analysis was done in the Xpower Analyzer by Xilinx.

• Backend Design Of 16 bit Fast Adder (July-

August 2011).

In this short project the tool used was Cadence Virtuoso Schematic Editor. The basic

library cells were designed and the layouts of the same were drawn. By using the

same basic cells the 16 bit fast adder was designed using the carry look ahead

algorithm and also by tree algorithms.

• System Controller (October

2010).

In the system controller the Schmitt trigger was used which can control ANY electronic

system, which is used for upper and lower limits of control, this design was also

implemented on PCB, and was tested successfully.

• Autonomous Robotics (December 2009

onwards).

Line follower and obstacle avoider has been designed with microcontrollers 8051 and

ATmega32 both individually; the programming was done in Embedded C.

• Running LED’s

(September 2009).

For running LED’s the simple JK flip-flop circuit was used to perform the action of

counter, which was then given to LED output, the design was implemented and tested

on PCB.

TOOLS, INSTRUMENTS USED AND PROGRAMMING LANGUAGES

1. Tools:

MATLAB, NCSim (Cadence), Virtuoso (Cadence), ISE (Xilinx), ModelSim, Eldo (Mentor

Graphics), Design Compiler (Synopsys), SoC Encounter (Cadence), Sentaurus (Synopsys), VNL

(Quantumwise), VASP, Gaussian, Proteus, Eagle, COMSOL Multiphysics.

2. Instruments Handled:

I. 4200 – SCS Parameter Analyzer (KEITHLEY).

II. SpinNXG – P2 (Apex Instruments).

III. Table Top Sputter Coater (MILMAN).

IV. Sentach Ellipsometer.

3. HDL’s and Programming Languages :

VHDL, Verilog, C, C++

ACHIEVEMENTS AND HONORS

• Awarded scholarship by JRD Tata Trust for academic excellence. (June 2010, June

2011)

• Active Participant in ASUS CAMPUS CONFERENCE 2011-2012.

• Dale Carnegie – Workshop on “Step up to Professional Excellence.”

• Vice Chairperson of IETE student Council for academic year 2010-2011.

• Won several awards in autonomous robotics.

• Conducted a seminar on robotics and SCADA systems.

EXTRA CURRICULAR ACTIVITIES

• Core Committee member of College sports council for the year 2010-2011.

• Being in the volleyball and cricket team of the class.

STRENGTHS

• Quick learner.

• Good communication skills.

• Flexible in team environment.

• Potential to take new responsibilities.

• Systematic work.

PERSONAL INFORMATION

: 15th January 1991.

Date of Birth

Gender : Male

Material status : Unmarried

Languages Known : English, Hindi and Marathi.

Hobbies : Reading, Listening Music, Playing.

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