CURRICULUM VITAE

SHEIKH JOHEB ANTAZ ALI Email: acex5b@r.postjobfree.com

Mobile: +91-973*******

PROFESSIONAL OBJECTIVE

To obtain an Entry level position as an ASIC DESIGN/VERIFICATION Engineer in a VLSI organization that

provides me an opportunity to grow and contribute to the overall success of the organization

SUMMARY

• B.TECH from AIEM, West Bengal in ECE and completed ASIC DV course from ExpertHDL, Bangalore

• Possess comprehensive knowledge & hands on experience in Verilog HDL, System Verilog and UVM

• Expert in developing constraint random and assertion based Verification Environment

• Good in writing Functional Coverage & Test cases

• Strong communication, collaboration & interpersonal skills with proficiency in grasping new technical concept

quickly and utilize them in effective manner

TECHNICAL SKILLS

Hardware Description Language: Verilog HDL, System Verilog

UVM (Universal Verification Methodology)

Methodology:

Protocol Knowledge: UART, AMBA AHB, AMBA APB

Scripting Language: Basics of PERL

Subject of Interest: Digital Electronics and CMOS

EDA Tools Used: QuestaSim, ModelSim (Mentor Graphics)

Operating systems: Linux, UNIX, Windows XP/7/8

EDUCATIONAL PROFILE

• B.TECH from AIEM under WBUT, West Bengal, in 2013 with 7.76 CGPA

• Higher Secondary from NDBM under WBCHSE, West Bengal, in 2009 with 67.2%

• Secondary from NDBM under WBBSE, West Bengal, in 2007 with 66.3%

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TRAINING

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• Institute Name: ExpertHDL Training & Consultancy Services

• Course: ASIC DESIGN & VERIFICATION

• Duration: August 2013 to April 2014

Academic Project

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• Name: Analog performance analysis of Double Gate MOSFET

• Tools used: Silvaco TCAD

Description: Based on the different characteristics of MOSFETs (i.e. threshold voltage,

transconductance etc.) this Performance Analysis has been done.

PROJECTS COMPLETED

Name: Asynchronous FIFO Design and Verification

Design Language used: Verilog HDL

Verification Language used: System Verilog

EDA Tool Used: QuestaSim

Description:

It is used for data synchronization when we are exchanging data across different clock domain and to

store the data. Here write & read clock frequency are different. Write pointer & write control works on

write clock frequency. Read pointer & read control works on read clock frequency.

Name: UART Design and Verification

Design Language used: Verilog HDL

Verification Methodology used: UVM

EDA Tool Used: QuestaSim

Description:

UART is a popular serial asynchronous communication to connect the processor and peripheral. It

essentially consists of transmitter, receiver and interrupt controller. Transmitter generates the UART

frame and sends the serial data with baud rate of maximum 3Mbps.

Name: AMBA APB Verification

Verification Methodology used: UVM

EDA Tool Used: QuestaSim

Description:

The APB is part of the AMBA protocol family. It provides a low cost interface that is optimized for minimal power

consumption and reduced interface complexity. The APB interfaces to any peripherals that are low bandwidth and

do not require the high performance of a pipelined bus interface.

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PERSONAL INFORMATION

Date of Birth: 16th June 1991

Sex: Male

Languages Known: English, Bengali and Hindi

Marital Status: Single

Present Address: #66 130 1,7th ‘c’ cross, 4th main, Jakkasandra new extention,

Bangalore 560034

Permanent Address: Vill Dhanyahana, P.O Illahipur, P.S Haripal, DIST Hooghly,

Pin code 712706, West Bengal

DECLARATION

I hereby affirm that all the documents stated above are true to the best of my knowledge

Date: 12/7/2014 sheikh joheb antaz ali

Place: Bangalore Signature of the Candidate

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