CURRICULUM VITAE

ABHISHEK MAITY

C-**/** DRDO Campus,

C.V Raman Nagar,

Bangalore

Pin: 560 093

890-***-****/944-***-****

acetf6@r.postjobfree.com

CAREER OBJECTIVE-

To associate with an organization which progresses dynamically and gives me a chance to update my knowledge gained through my Bacelor’s and Master’s Degree and enhance my skills, in the state of art technologies and be a part of the team that excels in work to words, the growth of organization and my satisfaction thereof.

STRENGTHS-

Dedicated and enthusiastic to face new challenges.

Ability to deal with ambiguity in defining activities and direction.

Highly motivated with a strong work ethic.

Self starter and ability to work in independent and collaborative environment.

EDUCATIONAL DETAILS-

Sl. NoQualificationUniversity/BoardSchool/College%age

ObtainedYear Of Passing1M-tech

(Electronics)

Visvesvaraya

Technological UniversitySir. M Visvesvaraya Institute of Technology

B’lore-562157

73.28%

(uptill 3rd sem)

2014

2BE

(Electronics & communication)Visvesvaraya Technological UniversityS.E.A College of Engineering &Technology,

Bengaluru-49

71.33%

2012312thCentral Board of

Secondary EducationKendriya Vidyalaya,

DRDO,

Bengaluru-560 09368.2%2008410thCBSEKVDRDO, Blore-9363%2006

INTERNSHIP AND PROJECTS UNDERTAKEN-

BE Project

Undertaken at Electronics and RADAR Development Esbt.(Min. Of Defence),Blore

Project title: Method of Moments as applied to microstrip patch antenna

Software used: Matlab 9.0

Project objective: It deals with computational electromagnetic process of modelling the interaction of electromagnetic field with physical objects and environment. It involves using computational approx to Maxwell’s eqn & is used to calculate antenna performance. It is used to calculate various parameters of antenna like return loss,VSWR,Input impedence,near field and far field components given the antenna dimensions.

2. M-tech 1st semester Mini Project:

Project title: low power CMOS 1bit full adder cell using gate diffusion input technique(GDI) (individual project)

Software used: Cadence virtuoso tool

Project objective: Here a low power full adder capable of operating down to 0.5volts have designed.The GDI technique have been used to generate the intermediate fuctions of xor and xnor. The transistor count is less than the conventional method.The new circuit is the most energy efficient cell.

3. M-tech 2nd semester Mini Project:

Project Title: Positive edge triggered D-flip flop design using NAND based SR latches.

Software used: Cadence virtuoso tool

Project Objective: To design a positive edge triggered D F/F using two NAND based SR latch stages then design the test circuit for the D-flip flop and study its operation characteristics and verification of its transient response and dc response.

4. M-tech final year project

Project Title: Unsync CMP:Multicore CMP architecture for soft error reliability

Software used: XILINX ISE 12.1, Modelsim6.2c

Project Objective: Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. We provide a redundancy based softerror resilient CMP architecture for both write-through and write-back cache configurations. We perform area estimation, power calculation, max freq of operation, worst case delay of design and synthesis report analysis.

TECHNICAL SKILLS-

Software Languages : Verilog,VHDL, C, C++,Microprocessor - 8086, Micro Controller-8051.

Hardware tools : Matlab, Cadence Virtuoso tool, Xilinx, Keil

MS Office tools : MS word, MS Excel sheet, MS Power Point, Ms Note, Ms Outlook

Operating systems : Linux red hat, Windows XP, Windows 7 and 8, MS DOS

Theoretical Concepts : VLSI design, Embedded systems, Operating Systems, Control Systems

Logic Design, Network Theory, OpAmps.

ACHIEVEMENTS-

Secured many prizes in various sports and cultural events held in school & college like spot creativity talk,Yoga and Athletics.

Have done various Technical paper presentations during intercollege events.

Have qualified BE with distinction and have secured award and Cirtificate of Commendation on LRDE raising day.

Received certificate of merit for having completed project work at “Electronics and Radar Development Establishment” (Ministry of Defence).

PERSONAL DETAILS-

Name : Abhishek Maity

Father’s name : Arun Kumar Maity

Mother’s name : Kathika Maity

Gender : Male

Date of birth : 11/6/1990

Languages known : English, Hindi, Bengali, Kannada

Marital Status : Single

Hobbies : Cycling, Photograph, Gaming, Surfing, Table Tennis

Nationality : Indian

DECLARATION:

I hereby declare that the above-mentioned information is correct up to my knowledge and bear the responsibility for the correctness of the above-mentioned particulars.

Place :Bangalore Name : Abhishek Maity

Note. Presently persuing 4th Sem. I will be completing in June/July 2014.

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