ANAMIKA

Mobile number: +91-805*******

Email Address: acesc3@r.postjobfree.com

OBJECTIVE

To build a career where I can utilize my current skill-set and expand it further and in turn contributing to

the growth of my peers and the organization.

EDUCATION

2012-2014 7.75 cgpa

Masters Of Technology (pursuing)

Thapar University

2007-2011 77.65%

Bachelor Of Technology

Lovely Institute of Technology,

Punjab Technical University

2006-2007 67.8%

Senior Secondary Examination - Class XII

SDA Senior Secondary School

I.S.C. Board

2004-2005 77%

Higher Secondary Examination - Class X

SDA Senior Secondary School

I.C.S.E. Board.

Skill Set and Interests

H/W and S/W Languages: C, C++, VHDL, Verilog

Software : ModelSim, Questasim, Xilinx, Lattice Diamond, Keil, Capture, Pyxis.

Scripting Language : Bash Shell scripting, tcl/tk scripting

Operating System : Windows and Linux Ubuntu

Other Skills : MATLAB, CMOS technology, FPGA

Experience

Design Engineer having hands on experience including HDL programming, FPGA semi-

custom design flow and Troubleshooting.

Industry : Semiconductors, Electronics

Designation : Design Engineer

Organization : Inxee Technologies Pvt. Ltd

Experience : 1 year (July 2011-June 2012)

Summer Internship/ Industrial Training

CoreEL Technologies Oc t 2013

Got training on VLSI system engineering and verification including hands on experience in RTL to

GDS flow.

DKOP LABS, NOIDA Jan-May 2011

Got training and hands on experience in digital designing, bash, tcl/tk, Verilog, CMOS technology.

EMBEX INSTITUTE, CHANDIGARH Jun -July 2009

Got training on HDL programming mainly VHDL.

LOVELY INSTITUTE OF TECHNOLOGY, PHAGWARA Jun-July 2008

Got training on PCB designing.

Thesis

Estimation of Node count, Execution speed and Power for Memetic algorithm in comparison with

dynamic algorithms.

Projects

M AJOR:

Design and implementation of Gesture Recognition using FPGA.

Embedded System based Performance Evaluation of SAN using 8051.

MINOR:

Design and implementation of IC 7495 using FPGA.

Designed Traffic Light Controller in Verilog.

Designed Array Multiplier in VHDL.

Designed and implemented Roulette wheel on PCB.

Academic Achievements/awards

Qualified GATE exam twice in 2012 and 2014 respectively.

Achieved academic excellence both at school and college level.

Published a paper titled "Reducing node count and computational time using different Crossover

Operators in Memetic Algorithm" in 3rd National Conference on "Advances in Metrology", Feb

2014.

Published a paper titled "Effect of various Crossover operators in Memetic algorithm on Multi-

input adders" in International Journal of Innovative Research in Electrical, Electronics,

Instrumentation and Control Engineering, Vol. 2, Issue 3, March 2014.

Extra-Curricular Activities

Worked as an Executive member in NSS camp.

Worked as an Organizing Committee member in National Conference, AdMet-2014.

Attended the seminar conducted by National Instruments on LabView tool in Noida in 2012

Attended the seminar conducted by Xilinx on IDE tool held in Noida in 2012

Volunteered in Gyan Manthan (Technology Fest) held in Lovely Institutes in 2007

Volunteered in Gyan Manthan (Technology Fest) held in Lovely Institutes in 2008.

The above statements are true to the best of my knowledge and belief.

ANAMIKA

Contact this candidate