CURRICULUM VITAE

Santhosh Kumar R

Email ID : acepvm@r.postjobfree.com

Mobile : +91-990*******

OBJECTIVE:

Intend to build a career with leading corporate with committed & dedicated people,

which will help me to explore myself fully and realize my potential, willing to work as a key

player in challenging & creative environment.

Work Experience:

One year six months of experience in the field of FPGA design.

Employer : EILABS INDIA PVT.LTD, BANGALORE.

Period : November 2012 to Till Date

Designation : Embedded Engineer.

Responsibilities : Verilog Coding using Quartus Tool, Schematic level Review,

Digital Design.

Worked as project trainee at MS. Ramaiah School of Advanced Studies, Bangalore from

September 2011 to July 2012.As a Design intern created a IP design for my M.Tech

Thesis which is based on Encryption and Decryption using AES and DWT.

EDUCATIONAL QUALIFICATIONS:

M.Tech in VLSI and Embedded Systems (CGPA 9.00 / 10) from Sri Siddhartha Institute of

Technology, Tumkur, Karnataka - 2012.

B.E in Instrumentation Technology (61.98%) from Siddaganga Institute of Technology-

2008.

Technical Skills:

Languages : Verilog, Microcontroller Pic16f877, ARM, Microprocessor 8085, 8086.

Software Proficiency:

Languages : C, C++, Software Testing, VB Script, QTP.

Operating Systems: windows 2000, windows Xp, Linux.

Tools : ModelSim, Quartus, Xilinx ISE, Synopsis DC, Primetime, DFT, Matlab

Subjects of Interest:

Subjects : Embedded Systems, Communication System, Power Electronics, Instrument

Transducers, VLSI Technology.

Certification: Modular Training Program (MTP) in Reliable Power Aware ASICs from

MSRSAS Bangalore.

Professional Project Details:

Title: PCIE based NIC card using WIFI and ETHERNET.(EI Labs India pvt Ltd)

Description: The PCIE card is based on ALTERA FPGA which has two features namely Wifi

and Ethernet used for controlling LAN with the speed of 10/100/1000 Mbps. This device

consists of five ALTERA FPGAS out of which two FPGAS are used as an MAC/ETHERNET

PHY and other two are used for data processing and controlling the data flow connected via SPI

to Control FPGA (NIOS-II). There are two modes, in mode-1 PCIe interface as input and

Ethernet interface 2 or Wi-Fi as output and in mode-2 Ethernet1 as input and Ethernet interface 2

or Wi-Fi as output. Control FPGA device has the configuration feature done through the AS

(active serial) or PS (passive serial) or FPP (fast passive parallel) to FPGA.

Technologies: ALTERA FPGA Implemented with NIOS-II processor.

Academic Project Details:

Reconfigurable Secure Image Coding Based on DWT and AES Processor (M .Tech Final

Year Project, Carried out at M.S. Ramaiah School of Advanced Studies, Bangalore)

Description: In this project combine the compression and encryption into single process. The

main objective of Reconfigurable secure image with DWT and AES is to get secure image with

minimum latency and speedy throughput. In this a new modified version of AES with DWT, to

design a compressed and secure image encryption technique, has been implemented. The color

image is converted into grayscale image and is compressed by 1-level using Discrete Wavelet

Transform, and then it is encrypted using AES. From the encrypted data image coefficients are

decrypted using Inverse AES and original image coefficients are recovered using IDWT. The

results of this coding algorithm with its embedded code and execution are so impressive that as

an efficient standard for secure image coding.

Tools used: Synopsis, Xilinx, Simulink.

Microcontroller Based Energy Theft Detector with Voice Output (B.E Final Year Project)

Description: The main aim of the project is to detect a power theft condition. The developed

system consists of two main sections Transmitter and Receiver. The transmitter consists of

Microcontroller PIC 16f877 which takes the responsibility of testing of theft and normal

operation of energy meter. If power is consumed by the load without running energy meter, the

control signal sent by the microcontroller triggers the transmitter to transmit signal to receiver.

When receiver gets signal from transmitter it indicates that energy theft has happened. A voice

chip is interfaced with receiver, which give the voice output of energy theft condition.

Papers Publication:

International conferences on my M.Tech research papers

“Reconfigurable Secure Image Coding Based on DWT and AES Processor: Brief Survey”,

International Conference on VLSI and Signal Processing, May 5th 2012.

“FPGA Implementation of a DWT and AES Processor for Secure Image Coding”,

International Conference on Electrical and Electronics Engineering, June 30th 2012.

National conferences on my M.Tech research papers

“A VLSI Implementation of a secure Image Coding Based on DWT and AES Processor”

National Conference on Emerging Trends and Developments in Information,

Communication, VLSI Design and Embedded Systems, March 21st 2012.

“Design and VLSI Implementation of a DWT and AES Processor for Secure Coding”

National Conference on Recent Advances in Electronics and Communication, May 18th

2012.

Personal Details:

Name : Santhosh Kumar. R

Father Name : Rangappa. P

: 17th March 1986

Date of Birth

E-mail Address : acepvm@r.postjobfree.com

Mobile : +91-990*******

Passport No : H3027570

: “Matha Pithrushree Nilaya”

Permanent Address

#224, TUDA Layout, Kalidasanagar,

Siragate, Tumkur – 572106

Gender : Male.

Languages : English, Kannada, Hindi, Telugu.

Hobbies : Interacting with people, Driving and Playing Cricket.

I hereby declare, that the above information and details provided by me are correct to

best of my knowledge.

Date: Yours faithfully

Place: Santhosh Kumar R

Contact this candidate