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Project Engineer

Location:
India
Salary:
2,75,000
Posted:
June 25, 2014

Contact this candidate

Resume:

Bharathkumar.v

Mobile: 988-***-**** acepqz@r.postjobfree.com

Objective

To succeed in an environment of growth and excellence and earn a job which provides me job Satisfaction and

self development and help me achieve personal as well as organization goals.

Summary

Engineer with Post Graduate Diploma in VLSI design and good academic record.Committed to the highest levels of

professionalism and excellent interpersonal skills. Demonstrated expertise in Verilog HDL and front-end & Back -End

Cadence based ASIC flow.

Skills Summary

Verilog.

C language

Good at Digital Concepts.

Linux Basics

Capabilit y of handling Synthesis & STA act ivit ies.

Basic knowledge in DFT.

Clear concepts of understanding, analyzing & fixing the timing vio lat ions.

Clear concepts of understanding timing, power and area constraints.

Clear concepts of understanding physical Design.

Project Experience

PROJECTS – POST GRADUATE DIPLOMA IN VLSI DESIGN

• Traffic Light Controller Design.

• Synchronous FIFO Design.

• Sequential multiplier.

Major Project – B.Tech Electronics & Communication Engineering

Mobile Signal Jammer:-

Mobile jammer is used to prevent mobile phones from receiving or transmitting signals with the base

stations. Mobile jammers effectively disable mobile phones within the defined regulated zones without causing

any interference to other communication means.

Requirements forthe Project:-

Domain : Wireless Technology & Embedded System.

Technology : Embedded C, Keil, Proload.

Certificate Course

Postgraduate Diploma (PG) in VLSI Design & Technology From Indian Institute Of VLSI Design and

Training(IIVDT) Bangalore, with industry standard project works.

Educational Qualifications

B.Tech in Electronics and Communication Engineering 2008-2012 with First -class fro m

Tirumala Engineering Co llege Hyderabad

Bharathkumar.v

Board of Intermediate Education (10+2) 2006 – 08 with First -class from Trinit y Junior Co llege,

Karimnagar.

Board of Higher Education (SSC, Khagaznagar) 2002 – 2006 with First -class from Sri Saraswathi

Sishu Mandir,

Achievements

• Won Mandal 3nd rank in SI writing in SSC

• Best stall award in college fest Pragma 2k10 .

Personal Assets

• Dedications towards work assigned and will try to give my best to it.

• Self-confidence, quick learning and adaptability.

• Good Leadership qualities and team spirit.

•Good knowledge about Technology and interest towards new learning.

Personal Profile

Father’s Name : Ramesh babu.v

Gender : Male

Marital status : Single

Date of Birth : 03-08-1991

Nationality : Indian

DECLARATION:

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Hyderabad Signature

Date : (BHARATH KUMAR.V)



Contact this candidate