DHIVYA SANKAR

**** * ******** *** ***** : 636-***-****

Chandler, AZ 85286 Email: acepoc@r.postjobfree.com

An Electrical and Computer Engineering graduate seeking a full time opportunity in the field of ASIC design/verification.

EDUCATION:

● Master of Science in Electrical and Computer Engineering May 2014

Georgia Institute of Technology, Atlanta, Georgia

● Bachelor of Engineering in Electrical and Electronics Engineering June 2012

Anna University, Chennai, India

WORK EXPERIENCE:

Graphics Circuit DA intern in Intel Corporation, Folsom,California May 2013 to Jan 2014

● Used Eagle, a software tool that uses a graphical interface to execute, manage, monitor and debug central runs for many

Functional Unit Blocks through various tool flows.

● Conducted central runs for tables such as FEV (Formal Equivalence Verification), PV (Performance Verification), LV

(Layout Verification) and RV (Reliability Verification). Major responsibilities included debugging tool issues and fixing

tickets filed by design engineers.

● Wrote a Perl script to compare golden and new library files for timing violations for successive steppings. Wrote

another script to set up a dashboard on a webpage that showed detailed status of various runs.

COMPUTER SKILLS:

● High level language : C, C++, Java, System Verilog, Perl, Tcl

● Design/Layout/Testing tools : Cadence, MATLAB, Nanohub, Synopsys Design Vision, Encounter and VCS

ACADEMIC PROJECTS:

DIGITAL MOS IC:

● Designed a 4*4 SRAM memory cell schematic (45nm PDT) and optimized the power consumption of the cell and

increased the frequency of operation to 1.5GHz using Cadence.

ADVANCED COMPUTER ARCHITECTURE:

● Cache simulator: Designed a parametric cache simulator and used it to design data caches well suited to the SPEC

benchmarks.

● Out of order Processor: Constructed a simulator for an out of order superscalar processor that uses the Tomasulo

algorithm and fetches N instructions per cycle. Used a simulator to find the appropriate number of function units and

fetch the rate for given benchmark.

● Cache Coherence: Designed a simulator that maintains coherent caches for a 4, 8, and 16 core processors.

Implemented the MSI, MESI, MOSI, MOESI, and MOESIF protocols for a bus based broadcast system.

COMPUTER AIDED DESIGN FOR VLSI (CAD):

● Formulated Synthesis reports of a standard semi custom VLSI cell using Synopsys design vision. Varied design

constraints such as area, frequency and clock to re optimize the design. Wrote Verilog IDCT (Inverse Discrete Cosine

Transform algorithm) code and simulated its functionality using Synopsys VCS.

PHYSICAL DESIGN AUTOMATION VLSI :

● Performed floor planning, placement and routing of the given net lists for different parameters of core using SoC

Encounter. Exported the gdsii file to Virtuoso, flattened and tested it for DRC (Design Rule Checking), LVS (Layout

Versus Schematic) and SPICE simulation.

RELEVANT COURSEWORK:

● Graduate Courses : Advanced Computer Architecture, Computer aided VLSI System Design, Digital Systems Test,

Digital MOS IC, Physical Design Automation VLSI, Advanced VLSI Systems, Digital design with Modern VLSI

Devices, Digital Communication

● Under Graduate Courses : Data Structures and Algorithms, Object Oriented Programming, Operating Systems,

Microprocessors and Microcontrollers, Linear Integrated Circuits, Digital Signal Processing

VISA STATUS: Permanent Resident

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