RADHA KRISHNA MURTHY GADDE

Specialization in: VLSI/ASIC Design and Verification/Computer Architecture

Email: aceoye@r.postjobfree.com www.linkedin.com/in/radhakrishnamurthy/ Phone: 215-***-****

* ***ta Montana, San Jose, CA Zip: 95314

EDUCATION

• North Carolina State University - M.S (Computer Engineering) 2012 – May 2014 GPA – 3.77/4

• Birla Institute of Technology and Sciences - B.E (Electrical and Electronics) 2006 – 2010 GPA – 8.0/10

COURSE WORK

• Digital ASIC design, ASIC verification, VLSI system Design, Architecture of Parallel Computers, Computer design and

Technology, Digital electronics, Analog Electronics, GPGPU Architecture, Electronic system level & physical design.

TECHNICAL SKILLS

• Programming/ Scripting languages - C, C++, Java, Verilog, System Verilog, SystemC, Python.

• Tools/ Protocols - Cadence Virtuoso, Hspice, Modelsim, Synopsys Design Vision, Sterling Distributed Order Management.

PROFESSIONAL EXPERIENCE

1) Software Developer – IBM India (ISL), Bangalore August 2010 – July 2012

• Worked as a technical support engineer for Sterling Distributed Order Management (Java based SCM product), resolving

product related issues reported by worldwide customers.

• Developed a lot of troubleshooting, communication and negotiation skills and handled several priority 1 scenarios.

2) Intern – Broadcom India, Bangalore July 2009 – December 2009

• Developed a tool for debugging the data routing of audio on a multimedia platform, currently used by firmware team while

running regression tests on the chips used in Blue ray DVD players using C#.

ACADEMIC PROJECTS

1) Verification of a pipelined LC3 microcontroller

• Designed a complete verification environment for a PIPELINED LC-3 microcontroller with a comprehensive

instruction set, using a reusable and fully layered test bench in System Verilog.

• All stages are functionally verified using both constrained random and directed testing to cover all the corner cases

and achieved exhaustive coverage using cover point and concurrent assertions.

2) Designing a hardware accelerator for Dijkstra’s algorithm

• Designed a hardware accelerator for Dijkstra’s algorithm, exploiting the parallelism that can be used in hardware.

• The RTL coding is done in Verilog and the design is synthesized using Synopsys Design Vision.

• Implemented several parallelization techniques to reduce total number of cycles taken for shortest path calculation.

3) TLM simulation of SOC

• Implemented a SOC platform including a CPU, AHB bus and a DDR DRAM memory controller in SystemC to run

TLM (Transaction Level Modeling) simulations.

4) 16x4 8T Dual port SRAM Design

• Designed a 64 bit dual port SRAM in 45nM CMOS, using Virtuoso cadence platform with DRC and LFD provided

by mentor graphics

• Made use of 8T bit cell to minimize the EDP and achieved 2.97 GHz operation at 1V in post-simulation.

5) Multilevel Cache Simulation

• Implemented a flexible cache and memory hierarchy simulator using Java programming and studied the

performance of memory hierarchies using the specified benchmarks.

• The simulator models a memory hierarchy with (1) an L1 data cache and (2) an L2 data cache and an optional

stream buffer in between the L1 cache and L2 cache.

6) Dynamic Scheduling using Tomasulo Algorithm

• Designed a Java based simulator to model an out of order, superscalar processor based on Tomasulo algorithm.

• This simulator implements Tomasulo’s algorithm with given Fetch/ Issue rate (N) and scheduling queue size (S).

• Analyzed the dependency of IPC (instructions per cycle) on scheduling queue size for various benchmarks provided.

7) Cache coherence Simulation in SMP

• Implemented various cache coherence protocols like MESI, MOESI, and DRAGON using Java based simulator,

driven by the input trace and a given configuration.

• Analyzed the dependencies of cache misses and invalidations on cache size, block size and various parameters.

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