MOBILE +91-779*******

+91-974*******

N K ALYAN KU MAR Home +91-944*******

L andline/M

Citizenship: INDIAN. DOB: 29/05/1990. Gender: Male. EMAI L aceo2a@r.postjobfree.com

MIT hostels, Manipal.

P resent

A ddress

Permanent Plot no 1-96, Sai Brindhavan Mansion, Flat no-002, Sainagar, Malkajgiri, Hyderabad, Andhra

P radesh.

A ddress

To serve an organization which provides challenging assignments to bring out the best of my creative

Objectiv

potential, which gives an environment to constantly learn new things and which supports me to excel in my

e

f ield of endeavor.

Educational Qualifications

Grade School / College Board / University Duration % / CGPA

10th ST.JOSEPH ENGLISH BOARD OF SECONDARY 2004-2005 74.5

M EDIUM H IGH SCHOOL E DUCATION,ANDHRA

PRADESH

12th NARAYANA JUNIOUR BOARD OF 2005-2007 87.3

COLLEGE I NTERMEDIATE

E DUCATION,ANDHRA

PRADESH

B.Tech K.S.R.M COLLEGE OF SR I VE NKATESWARA 2007-2011 65.37

E NG I N EE R I NG U N I V E RS I TY,T IR UPAT I

M. MA N IPAL I NST I T U TE MA N IPAL U N I V E RS I TY 2013-2015 7.67

T ech* O F TEC HNOLOGY

Branch of ELECTRON ICS AND CO M M U N ICAT ION E NG I N E ER I NG

E ngineering

Sem 1 Sem 2 Sem 3 Sem 4 Sem 5 Sem 6 Sem 7 Sem 8

Percentage 63.375 57.11 58.5 62.875 70.5 70.625 69 76.8 M.Tech Branch: D IGITAL ELECTRONICS AND ADVANCED COMMUNICATION CGPA : 7.67

1.VLSI Testing and 2.VLSI Physical Design and

Elective 3.Analog VLSI for Signal

Testability Verification P rocessing

S ubjects

ASIC D esign and verification, Processor Architecture, D igital VLSI Design, analog and digital design,

Areas of

D igital Communication.

I n terest

Skill Sets

Languages C, Verilog, Basics of System Verilog.

Tools Mat lab, ModelSim, CADENCE (Virtuoso, NCSim).

Operating System Windows 7, XP, vista, Linux.

Technical Activities

1

PROJECT 1: M .Tech 1 year project - B uilding Verification Environment To Verify Memory controller using System

Verilog Layered Test Bench.

D escription : B uilt the system Verilog class based layered test bench with coverage driven constrained random stimulus

features to verify the parallel Read/Write Memory controller.

PROJECT 2:B. Tech Main project: I mplemented a project titled I mage ret rieval using color and textu re using

M ATLAB.

PROJECT 2:B. Tech M ini P roject: Performance Considerations in Low Power CMOS Designs.

PROJECT 4: Implemented a paper on CMOS Full-Adders for Energy-Efficient Arithmetic Applications.

Additional Activities

1. Attending industrial t raining on Digital and Analog VLS I design (certified course) by Ka rnataka

M icroelectronics Design Centre, Manipal (six months t raining) along w ith t rainees of company

( Ka rmic).

2. Organizing commit tee member of "ENERGY 2009" a state level symposium in KSRM, Kadapa.

Achievements

1. I got 97.7 percentile in GATE-12 and gate score 504 with Rank (AIR: 5120) GATE-13.

2. Won district level chess championship (10th class).

3. Represented my college in state level chess tournament and stood in third position.

4. Won Rubik’s cube and Puzzle solving competition in college

R eferences

1. Professor Dr. Dattaguru.v.kamath M IT, Manipal. Mobile:+91-961******* email:aceo2a@r.postjobfree.com

2. Professor Dr. M.Sathish Kumar, MIT, Manipal. Mobile:+91-948******* email:aceo2a@r.postjobfree.com

The above information provided by me is t rue and have all the relevant documents to authenticate the same.

N KALYAN K U MAR

2

3

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