CURRICULUM VITAE

Harish Padma Contact no: 91-953*******

Email:

acenwx@r.postjobfree.com

CARRIER OBJECTIVE:

Looking for a challenging career which demands the best of my

professional ability in terms of, technical and analytical skills, and

helps me in broadening and enhancing my current skill and knowledge. And

want to achieve excellence in the job assigned to me while continuously

gaining knowledge and learning new things.

ACADEMIC QUALIFICATIONS:

Qualification Board / University Year of Aggregate

passing percentage

M.Tech CVR college of engineering and Pursuing 85.8%

(VLSI System technology, 2nd year

Design) Under JNTU, Hyderabad

B. Tech (E.C.E) Vignan Institute of Technology 2011 64%

&science,

Under JNTU, Hyderabad

Diploma (E.C.E) TRR college, S.B.T.E.T Board, 2008 59%

Hyderabad

S.S.C. Gnana vagdevi vidyalayam, A.P 2005 74.6%

state Board

EXPERINCE:

* Trainee engineer at Reliable techno system pvt ltd, Hyderabad

Duration: 3 months (May to till August 2014)

* One week training in ASIC Full Custom Design at C.V.R College of

technology, Hyderabad.

Duration: April -May2013

ACADEMIC PROJECTS:

MTECH PROJECT

PROJECT : Implementation of Low cost FIR filter design

using Truncated Multiplier

ORGANISATION : CVR College of engineering and technology

DURATION : February 2014 to till date

TOOLS USED : Xilinx ISE Design Suite 13.2

LANGUAGE : Verilog HDL

Configuration Board : Virtex 5(XUPV5-LX110T)

DESCRIPTION : Multiplication is one of the most area consuming

arithmetic operations in high performance circuits, normally when you

multiply two N bit numbers the output of the multiplier will be 2N bit

but we don't require full precision output in some times, in that

cases we will preferred special type of multiplier named as "Truncated

multiplier" which will produce the output as N bit thus it decreases

hardware resources, so Truncated multiplier offers significantly

Improvements in area power delay, truncated multiplier we are using in

FIR filter design and thus fir filter also will have improvements in

area power and delay compared to Normal FIR filters.

FIR filter has been designed in Verilog code and it is implemented in

VIRTEX 5 board FPGA

BTECH PROJECTS

* PROJECT (MAIN) : Automatic Number Plate recognition

ORGANISATION : Vignan institute of technology &science

DURATION : 3 months (December -2010 to march -2011)

DESCRIPTION : The main aim of our project is used to recognise the

Number

Plate based on MATLAB

* PROJECT (MINI) : Temperature Indicator &controller using

Thermistor

ORGANISATION : Guts electro Mech Pvt ltd.

DURATION : 2 months (august -2010 to October -2010)

DESCRIPTION : The main aim of our project is used to display the

Room Temperature.

It is mainly based on principle of Thermistor

negative Resistance

Characteristics.

ACADEMIC SEMINARS:

* New Revolutionary material In Electronics (GRAPHENE).

* Green Electronics.

* Ferro Electric Memories.

TECHNICAL SKILLS :

* OPERATING SYSTEMS : Windows /XP/2000,Ubuntu linux

* TOOLS HAVE BEEN USED : XILINX ISE9.2i &14.2, Synthesis tool:

X.S.T,

Simulator Tool: ISE,QUESTA SIM 10.0

* CADENCE : Schematic Entry, Layout(virtuoso)

* CORE LANGUAGE : VERILOG,VHDL

* Asic design flow and Fpga design flow

PERSONAL PROFILE :

Name : P.Harish

Father name : Gangadhar

Date of Birth : 15-03-1989

Marital status : Unmarried

Nationality : Indian

Languages : English, Telugu and Hindi

Hobbies : Listening Music, Playing Indoor Games

(Caroms)

Address for correspondence : House No. 2-4-600,

Road no: 9/A,

New Nagole Colony,

Behind Andhra bank,

Nagole, Hyderabad, A.P.

DECLARATION :

I hereby declare that the above information is correct to the best of

my knowledge.

Place: Hyderabad.

Date:

(P.Harish)[pic]

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