RIYAZ MANSUR

(M) 903-***-****, Email: acekw0@r.postjobfree.com (Bangalore)

Career Focus

To make a career in the VLSI domain by utilizing the knowledge gathered in educational,

professional and social life to further enhance the skills by applying them all in an organization

that provides opportunities & appreciation.

Highlights

.

CTS and its Quality check

DFT (Design for Test).

Clock Algorithm

Combinational and Sequential Stuck at Fault

Knowledge of Static & dynamic RAM .

Modelling and Simulation

ASIC and FPGA design flow.

ATPG, JTAG

Writing RTL code.

BIST (Built In Self Test).

Verilog, VHDL, SystemVerilog (Xilinx,

CMOS digital logic design.

QuestaSim).

Concept of 2nd order effect in CMOS

Programming language C, OOPs concepts.

Xlinx ISE 13.1, Modelsim, Mentor Graphics and

Tanner.

Timing Analysis for Physical design

Education

M.Tech in VLSI Design from Nirma University, Ahmedabad in 2013 with 66.6% (7.16 cpi)

B.E in Electronics and Communication from Sardar Patel University, Vallabh Vidhya Nagar in

2010 with 64.81%(6.67 cpi)

12th from Seth H.C.Parekh Navsari High School, Navsari in 2006 with 81.60%

10th from Seth H.C.Parekh Navsari High School, Navsari in 2006 with 81.43%

Experience

Smart chip design Pvt. Ltd. Bangalore (4 month) - I have done some industrial level projects

in Verilog, System-Verilog like-

Major Combinational and Sequential Logic design in Questasim using Verilog.

DUT (Switch) verification with Interface, Environment class, Driver, Receiver and Score board.

(In System-Verilog).

Projects

PROJECTS DURING M TECH

Cryptography Algorithm On Reconfigurable Hardware

Tools & technology : Xilinx ISE 13.1,Modelsim,Chipscope pro

Design and Developed “16-bit RC6 Cryptography algorithm” using VHDL language in Xilinx ISE

13.1

Coded the same project in Matlab

Performed simulation using Modelsim

Analysis of synthesis report

Implemented on Spartan 3,Spartan 3E,Vertex 5

PROJECTS DURING B.E

IMPLEMENTATION OF FIFO

RTL Coding of FIFO using Verilog HDL in Questasim tool

Developed test bench for the same

Additional Information

ACHIEVEMENTS:

Awarded First Prize for the Best Project entitled CRYPTOGRAPHY ALGORYTHM

IMPLEMENTATION in M.Tech. Electronics and Communication (VLSI) in Project Exhibition

cum Competition Organized by Institute of Technology, Nirma University.

Got 43.33 marks (96.67 percentile) in Gate 2011.

EXTRA CO-CURRICULAR ACTIVITIES:

Attended expert lecture by S.C.Bose Sir from CEERI Pilani on Basics of Analog Design.

Attended expert lecture by Pro.Chetan Parikh on DAC Architectures.

Personal Vitae

RIYAZ MANSUR

Name :

Indian

Nationality :

8th June 1989

DOB :

B/10.Shiv- Parvati Krupa soc,

Residency Add. :

Nr. Vidhyakunj High School, Jamalpore,

(Permanent)

Navsari-396445, Gujarat, India

English, Hindi, Gujarati (Read and Write)

Known Languages :

Playing Volleyball, Cricket, Watching Movies.

Hobbies :

I hereby declare that the information given above is true to the best of my knowledge & belief.

Date RIYAZ MANSUR

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