SOUMYA SHETTY

Email:acec1j@r.postjobfree.com

Mobile Phone : +91-988*******

OBJECTIVE

Seeking a challenging work in the field Analog/Mixed Signal layout that encourages continues

learning and providing exposure to new ideas, which stimulates professional and personal growth.

TECHNICAL SKILLS

o Programming Languages: Unix Shell, SKILL, PERL

o Layout tools: Cadence virtuoso layout editor.

o LVS/DRC tools: Assura LVS/DRC/RCX, K2 Verification

Simulation Tools: NGSPICE, CADENCE(CDB and Open access – OA)

o

o Application Software: MS-Office, Open Office (LINUX), Design-Sync (Solaris)

PROFESSIONAL EXPERIENCE

o 2+ years of experience as Analog and mixed signal layout engineer in “KarMic” (Karnataka

Microelectronic Design Centre Pvt, Ltd. Manipal, Udupi, Karnataka, India.

o Worked on BIASING, ADC, DAC, BGR, LDO, REFSYS, TESTMUX, OCILLATOR etc.

o Supported multiple Full chip LVS/DRC.

o Undergone training from Dr. S.S. Mahant Shetti for 6 months in Analog and

Digital Domain at “Karmic Training and Research Center”, Nesargi.

PROJECTS

PROJECT 1: 65nm Technology

Worked on amplifiers and Pre-driver,Biasing modules from scratch and also

Description

incorporated the layout design fixes.

Analog Layout Design Engineer

Role

1.Matching,Floor planning,routing,Power

Contribution Responsibility

planning.

2.Done Assura LVS/DRC/Power plots.

3.Worked on layout modifications for design

changes.

4.Worked on auto-route for digital blocks.

5.Worked on metal fixes for METAL PG

6.Supported for chip level LVS & DRC

7.Trained the fresh engineers in the team

Development/Productivity Cadence Virtuoso Layout editor.

Tools

18 months

Period

Team Size 5

PROJECT 2: 90nm Technology.

Worked on Biasing circuits, LDO,driver blocks from scratch and also incorporated

Description

the design changes in 90nm technology.

Analog Layout Design Engineer

Role

1.Matching,Floor planning,routing,Power

Contribution Responsibility

planning.

2.Done Assura LVS/DRC/Power plots

3.Worked on layout modifications for design

changes.

Cadence Virtuoso Layout editor.

Development/Productivity

Tools

Period 8 months

Team Size 3

PROJECT 3: 150nm Technology

Worked on various modules like Amplifiers,level shifters,Biasing circuit,schmitt

Description

trigger from scratch and also worked on layout design changes for IO

Buffer,BUCK,ADC,DAC, LDO,power management and audio modules.

Analog Layout Design Engineer

Role

1.Matching,Floor planning,routing, Power

Responsibility

Contribution

planning.

2.Done Assura/K2 LVS,K2 DRC,Power

plots,Antenna checks,net tag check,Doc view

creation.

3.Worked on Layout design changes.

4.Worked on auto-route for digital blocks.

5.Worked on critical resistor matching block from

scratch.

6.Worked on metal fixes for METAL ONLY PG

7.Worked on parasitic reduction in layout.

8.Trained the fresh engineers on 65nm/90nm

technologies.

Cadence Virtuoso Layout editor..

Development/Productivity

Tools

4 months

Period

8

Team Size

TRAINING & SEMINARS:

Trained fresh engineers on analog layout

concepts.

Given seminars on process flow.

EDUCATION

E&C Engineering (B.E), St. Joseph Engineering College, Mangalore, obtained

72% in the year 2010.

PERSONAL DETAILS

Name : Soumya Shetty

Father’s Name : Bhaskar Shetty

Mother’s Name : Indira Shetty

Date of Birth : 28.05.1986

Languages known : English, Kannada, Tulu

DECLARATION

I here by declare that the details furnished here are true to the best of my knowledge.

Place: Manipal Soumya Shetty

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