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USHASREE BOMMU Email: ace8yb@r.postjobfree.com

*-*-***, **********, *********** Cell: 093*-***-****

Hyderabad – 500058. Landline: 040-********

SUMMARY

• 4 years of total industry experience with Masters in Electrical Engineering from Ohio State University.

• 2 years of experience in RTL Design and SoC Verification using HDLs and Verification Methodologies.

• Sun Certified Java Programmer with 2 years of experience in object-oriented analysis, design and

development applications using C and C++.

• Good understanding of ASIC and FPGA design flow.

• Proficient in writing RTL design codes using Verilog, System Verilog, VHDL and AHDL.

• Hands on experience in writing verification codes using System Verilog, UVM and OVM.

• Extensive experience in using industry standard EDA tools for the front-end design and verification.

• Knowledge of Advanced Micro Controller Bus Architecture (AMBA) protocols like AHB, APB and

AXI.

• Experience in using AMBA Designer (Ad Canvas) tool to generate RTL fabrics, using Cadence

Interconnect Workbench (IWB) tool to generate verification environment in e and sv and running manual

and automated tests to validate the fabrics using Cadence Incisive Simulator.

• Familiar with adding the standalone fabric tests to vsif file and filing regression using vmanager.

• Good hands on working with the Clearcase tools in UNIX environment.

• Basic knowledge of Computer Architecture.

SKILLS

HDLs Verilog, VHDL, AHDL.

HVL System Verilog.

TB Methodology UVM, OVM.

Cadence Incisive Simulator, Ad Canvas, vmanager, IWB, UXE, NCSIM,

EDA Tools

Questasim, Modelsim, Xilinx ISE, Altera’s Quartus II, IRSIM.

Domain Digital Design & Verification.

Knowledge RTL Coding, FSM based design, Simulation and Synthesis.

Programming Basic C and C++.

EDUCATION

MS in Electrical and Computer Engineering, Graduated: August 2010

The Ohio State University, Columbus, Ohio, USA

GPA: 3.76/4.0

BTech in Electrical and Electronics Engineering, Graduated: May 2007

Pondicherry University, Pondicherry, India

GPA: 8.7/10.0

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PROFESSIONAL QUALIFICATION

SoC Verification Engineer: Dec 2012 – Nov 2013

Cadence Design Systems, Bangalore, India

Advanced VLSI Design and Verification Engineer: Jan 2012 – Nov 2012

Maven Silicon, Bangalore, India

Consultant: Jan 2011 – Dec 2011

Sears Holdings Home Services, Chicago, IL, USA

Assistant System Engineer: Sep 2007 – Dec 2008

Tata Consultancy Services, Bangalore, India

PROJECTS

Samsung DUT- Generation and Validation using excel based IWB environment, Cadence Design Systems,

Sep 2013 – Nov 2013

• Generated the NIC 400 axi3 18x8 DUT fabric as per the specified clock domains using the Ad canvas

tool.

• Developed the ipxact based IWB environment by invoking the glue tool and executing the ipxact

javascript.

• Made sure that the ipxact IWB tb top with the VIPs auto connected to DUT fabric compiles and

simulates with all test suite test cases.

• Created the excel flow based IWB environment by invoking the glue tool and executing the excel

javascript.

• Modified the excel IWB test bench top with the DUT fabric manually instantiated and connected to

VIPs and a clock-reset generator driving different clocks and resets required for the fabric and VIPs.

• Simulated the final modified excel based IWB tb top with all test suite test cases.

• Moved the standalone test suite test cases to vsif file for regression testing using vmanager.

• Worked on various Clearcase tools in the UNIX environment to check in and merge the local view

changes to the main view.

Marvell ARM AMBA fabrics – Generation and Validation using ipxact based IWB environment, Cadence

Design Systems, May 2013 – Aug 2013

• Generated the UVM E and UVM SV based IWB environments for AMBA (AXI, AHB, APB) and

Marvell fabrics using IWB command and Glue GUI.

• Validated and reported the status of manual and auto test cases of the fabrics.

• Carried out standalone testing of the fabrics for quick validation results and moved the tested fabrics to

vsif file for regression testing using vmanager.

• Made use of Clearcase tools in the UNIX environment to merge the local changes to the main view.

Verification Acceleration Kit – RTL Design and Verification using UVM SV, Cadence Design Systems, Feb

2013 – April 2013

• Analyzed the UVM code of UART UVC and integrated the UVC with the va kit environment.

• Developed the TX/RX sequences from Purespec AXI VIP to UART UVC via the va-kit DUT.

• Created different read/write test scenarios between AXI and UART VIPs.

• Replaced the open core UART16550 verilog code with SV design code and tested the same in va-kit.

• Made use of Incisive Simulator/NCSIM to analyse the simulation results in the batch and gui mode.

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• Used Unified Xccelerator Emulator (UXE) tool to check if the UART SV design is synthesizable and

ran the compiled result on Palladium XP Emulator.

DDR3 Controller and NIC400 fabric – Integration and Verification using IWB environment, Cadence

Design Systems, Dec 2012 – Feb 2013

• Generated the NIC400 fabric with AXI3 interfaces using AMBA Designer Canvas (Ad Canvas) tool.

• Used Interconnect Workbench (IWB) command to create UVM SV testbench (TB) for NIC 400 fabric.

• Instantiated the DDR3 design IP in the TB and stitched the NIC400 with the DDR3 memory controller

using AXI3 interfaces.

Router 1x3 – RTL Design and Verification using Verilog and OVM, Maven Silicon, June 2012 – Nov 2012

• Architected the Verilog RTL design of router components and passed appropriate stimulus from the TB.

• Synthesized the RTL design and analyzed the simulation results of test bench using Xilinx ISE.

• Constructed the class based verification environment using OVM.

• Made use of Modelsim as the EDA tool to view the OVM verification results in the gui mode.

Dual Port RAM – RTL Design and Verification using Verilog and System Verilog, Maven Silicon, Jan 2012

– May 2012

• Formulated the RTL design code and test bench of Dual Port RAM using Verilog.

• Performed the synthesis and timing analysis of the design in the Xilinx ISE environment.

• Architected the class based verification environment using System Verilog.

• Used Questasim as the EDA tool to analyze the SV verification results in the gui mode.

Microprocessor Datapath – RTL Design using VHDL, The Ohio State University, April 2010 – June 2010

• Constructed the basic generic unit and tailored three such units along with the carry chain unit to

perform 16 arithmetic and logical operations of a 1-bit ALU.

• Structured eight components of 1-bit ALU to form 8-bit slice ALU.

• Coded the functionality of 16 bit dual ported register and assembled it with I/O buses and 8-bit slice

ALU to form the datapath of the microprocessor.

Keypad Scanner System – RTL Design using AHDL, The Ohio State University, Jan 2010 – Mar 2010

• Formulated the schematics and AHDL code of Keypad Scanner Components (Column Scanner, Row

Encoder, Output Data Latch, System Controller, Keypad Simulator and Clock Divider).

• Conducted the simulation and timing analysis of the design and verified its functional correctness in

Altera’s Quartus II environment.

• Loaded the design on CPLD (EMP7128SLC84-7), generated the net list, wired up the keypad to the

appropriate pins and tested the circuit.

Sears Holdings Home Services Team, Consultant, Jan 2011 – Dec 2011

• Attended the JAD sessions with the Business Analysts, Quality Analysts, Iteration Manager and the

offshore team to get a clear understanding of the business requirements and estimates for each story.

• Participated in the iteration meetings with the entire SHS team, kick off meetings with the BA and stand

up meetings with the offshore team to update the stories and the jiras handled in iteration.

• Prepared design document to formulate the business and functional requirements in the form of use

case, sequence and activity diagrams.

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• Configured the development environment.

• Developed the code.

• Attended the production issues in the code.

Global Human Resource Team of JnJ, Tata Consultancy Services, Sept 2007 – Dec 2008

• Developed Inbound and Outbound UI interfaces between GHRT and its clients using webMethods.

• Handled the webMethods middleware that supported various coordination patterns like

publish/subscribe, request/reply to ensure guaranteed delivery of messages between source and target

systems.

• Developed Inbound and Outbound UI interfaces between GHRT and its clients using webMethods.

• Handled the webMethods middleware that supported various coordination patterns like

publish/subscribe, request/reply to ensure guaranteed delivery of messages between source and target

systems.

• Provided application support to AP2PLE team of JnJ for proper compliance between corporate systems

(Ariba, Shared Services AP) and webMethods.

• Documented the reports describing the flow of interfaces, framework services involved, data

transformation and mapping between source and target fields.

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