Prithvi Raj M S Address: SriDurgaDevi

nilaya

E-mail: ace7h2@r.postjobfree.com near Rangayyana Bagilu,

Mobile No: +91-906******* Chitradurga-

577501.

OBJECTIVE:

To step into the corporate as a creative and unique associate engineer in VLSI with

my supporting technical skills and to utilize my optimistic and sensible way to take

the industry to be the pioneer there by getting monopoly over its products and

services.

EDUCATIONAL QUALIFICATIONS:

DURATION COLLEGE / UNIVERSITY CGPA /

%

OF COURSE

2013-2015 Manipal University Jaipur

7.23CGPA

Master of Technology (Micro Electronics)

2009-2013 GMIT, Davangere

Bachelor of Engineering

(Electronics and Communication Engg.)

68.92%

(Visveswaraiah Technological University, Belgaum)

2007-2009 BRUHANMATHA PU COLLEGE, Chitradurga 77.5%

PUC-2nd year

(Karnataka Pre-university Board)

2006-2007 DON BOSCO High School, Chitradurga 90.24%

SSLC/10th Std.

(Karnataka Secondary Board)

TECHNICAL SKILLS :

Languages : Verilog, 8051, System Verilog, C

•

Software tools : Questasim, Xilinx ISE,

•

OPERATING SYSTEMS : Linux (Ubuntu), Windows XP/7

•

Verification Methodologies : UVM

•

PERSONAL SKILLS:

• Zeal to accept challenging work environment, Dedication towards work.

• Good communication skills.

• Pragmatic, Self-Motivated and a good Team player.

• Good Analyzing skills, Communication Skills, Good Listener and Learner.

EXTRA CURRICULAR ACTIVITIES:

• Presented paper on 5G technology.

• Selected for States in Cricket at the age 13,15,17,19.

• Served as School Pupil Leader in High School days.

• Served as Class Representative for 2nd, 4th year of BE.

• Served as event coordinator For DELTA-12.0

• Served as sports secretary at college level during year 2012.

TRAINING UNDERGONE:

• Training session on “C Language”.

• Training session on “EMPLOYABILITY SKILLS” by GMIT College.

• Pursuing course of VLSI-RN from Maven Silicon Softech Pvt Ltd.

PROJECTS:

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: System Verilog

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and routes

them to one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

• Architected the design

• Implemented RTL using Verilog HDL.

• Architected the class based verification environment using system Verilog

and UVM.

• Verified the RTL model using System Verilog.

• Generated functional and code coverage for the RTL verification.

• Synthesized the design.

Dual port RAM Soc - RTL Design and verification with UVM

HDL: Verilog

HVL: System Verilog

EDA Tools: Questasim and ISE

Description: Ram Module having size of 3K X 63 and supports simultaneous

Read and Write.

Responsibilities:

• Implemented the Dual Port RAM SoC using Verilog HDL.

• Architected the class based verification environment using SV and UVM.

PROJECT IN M.Tech:

UART- IP Core – Verification

HDL: Verilog

HVL: System Verilog

EDA Tools: Questasim and ISE

Description: The UART IP core provides serial communication capabilities, which

allow communication with modem or other external devices. UART will operate in

three different modes – Simplex mode, Full Duplex mode and loopback mode.

Responsibilities:

• Architected the class based verification environment in UVM.

• Verified the RTL model using System Verilog.

• Generated functional and code coverage for the RTL verification.

• Features verified

• Loop Back Mode, Full Duplex Mode and Half Duplex Mode.

• Transmission and Reception with Parity and Stick Parity Error.

• Break Error, Frame Error and Overrun Error.

PROJECT IN BE:

Name of the Project: ”GSM & GPS BASED ACCIDENT LOCATION AND

INTENSITY INFORMATION SYSTEM”.

Tool: AT89c51 micro-controller, Embedded C, Kiel µvision2, Flash Magic.

Team Size : 4.

Project Summary: GSM & GPS Based Accident location and intensity

information system uses GSM module to send the messages and GPS

module to track the location where accident has occurred .This project will

tell us about the intensity of the accident occurred by using a pressure

sensor to the vehicle. Also gives the information with how much speed

vehicle hits and according to that, intensity of the accident can be detected.

• Done At: G.M Institute Of Technology, Davangere.

PERSONAL PROFILE :

• Father’s Name : Sainatha Rao.

• Mother’s Name : Manjula.

• Date of Birth : 13-Apr-1991

• Nationality : Indian.

• Gender : Male.

• Languages known : English, Kannada, Hindi, Telugu

• Hobbies : Browsing, Playing games, Listening music.

Declaration :

I certify that to the best of my knowledge and belief, the above mentioned

information correctly describe my qualification. Further, I certify that given an

opportunity, I would work to the best of my abilities and your satisfaction.

Yours Sincerely,

Place: Bangalore (Prithvi Raj

M S)

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