OBJECTIVE

Seeking a Physical Design Engineer position to utilize my skills and

abilities in the Industry that offers Professional growth while being

resourceful, innovative and flexible.

PROFESSIONAL TRAINING

Completed training in VLSI Physical Design on Cadence Tools from

Institute of Silicon Systems Pvt. Ltd, Hyderabad.

Course outline

VLSI Fundamentals, CMOS Basics, Digital Design, Floor Planning, Power

Planning, Placement and Routing, clock tree synthesis, static timing

analysis, cross talk analysis, IR Drop Analysis and Physical Verification.

TOOLS

Experience in physical design of 130nm and 90nm technologies using Cadence

tools

V Cadence SOC Encounter - Floor Planning, Place & Route, and clock tree

synthesis

V Encounter Timing System - Static Timing Analysis and Crosstalk Analysis

V RTL Compiler- Logic Synthesis

V Assura - Physical Verification

EDUCATION

Aggregate Year of Institute Course

passing

86.0% 2011 SICET, Hyderabad M. Tech (DECS)

68.5% 2007 NIET,Hyderabad B. Tech (ECE)

76.8% 2003 Rajadhani College, Hyderabad Intermediate

72.4% 2001 Siddhartha high School, S.S.C

Hyderabad

PROJECTS

> Physical Design

Project 1: PCI_DATA (top level)

Objective : Timing driven layout

Tools : SOC Encounter

Gate count / Area : 128,961 / 1,572,915 um2

Macros / STD Cells : 12 / 24,450

No. of Clocks : 4

Frequency : 149.9 MHz

Utilization : 52.1 %

Technology / Layers : TSMC 0.18 microns / 5 Metal Layers

Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO,

Trial Route, Timing Analysis, CTS, Detail Routing. To achieve 0 %

congestion at trial route stage.

Project 2: (block level)

Objective : To observe the usage of metal layers

Tools : SOC Encounter

Gate count / Area : 7,701 / 76,856 um2

STD Cells : 2477

No. of Clocks : 3

Frequency : 333 MHz

Utilization : 70.1 %

Technology / Layers : UMC 0.18 microns / 5 Metal Layers

Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO,

Trial Route, Timing Analysis, CTS, Detail Routing. To observe the

relation between core utilization, wire length and number of metal

layers.

Project 3: SPECTRUM (Block level)

Objective : Timing Driven Layout

Tools : SOC Encounter, QRC, ETS

Gate count / Area : 296,296 / 1,508,801.9 um2

Macros / STD Cells : 12 / 25195

No. of Clocks : 17

Frequency : 200 MHz

Utilization : 87.3 %

Technology / Layers : TSMC 0.13 microns / 5 Metal Layers

Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO,

Trial Route, Timing Analysis, CTS, Detail Routing, RC extract, STA.

> Logic synthesis

Project 1 : An 8-bit synchronous counter with asynchronous reset.

Clocks / Frequency : 2/200MHz

Role: Generated Constraint file, TCL file and Performed Wire load and

Zero Wire load model.

Project 2: A 256-bit counter

Role: To find the frequency of operation of the counter and generate

the constraints file, TCL script and close timing by performing wire

load and Zero wire load model.

> Layout

Tools : Virtuoso

Design : Basic gates

Role: Designed Layouts for Inverter, Nand, Nor, And, Or gates and

Latch.

Academic Projects

> A Efficient Framework for Channel coding in high speed links.(M. Tech)

. Scope of the project:

This project explores the benefit of channel coding for high-speed

backplane or chiptochip interconnects, referred to as the high-speed

links. Although both power constrained and bandwidth-limited, the high-

speed links need to support data rates in the Gbps range at low error

probabilities. The resulting framework is used to identify the conditions

under which standard error control codes perform optimally, incur an

impractically large overhead, or provide the optimal performance in the

form of a single parity check code. For the regime where the standard

error control codes are impractical, this thesis introduces low

complexity block codes, termed pattern-eliminating codes (PEC), which

achieve a potentially large performance improvement over channels with

residual ISI. The simulation results show that the simplest PEC can

provide error-rate reductions of several orders of magnitude, even with

rate penalty taken into account. It is also shown that

channel conditioning, such as equalization, can have a large effect on

the code performance and potentially large gains can be derived from

optimizing the equalizer jointly with a pattern-eliminating code.

Although the performance of a pattern-eliminating code is given by a

closed-form expression, the channel memory and the low error rates of

interest render accurate simulation of standard error-correcting codes

impractical

> Compact receiver ESMC project (B. Tech)

. Scope of the project:

. Lightweight - compact - user-friendly, optimized radio monitoring from

0.5 MHz to 3000 MHz.ESMC is a heterodyne receiver with a second IF of

21.4 MHz In spite of the compact design, No compromises have been made in

the operating concept. For reducing the total signal load, the tuners are

each provided with a tracking preselection filter. High-level mixers

ensure high immunity to intermodulation. The low oscillator reradiation

is the result of elaborate filtering. An advanced synthesizer concept

featuring a very low phase noise allows switching times of less than 1

ms. this permits highly efficient scanning and fast status assignment in

slave operation. Compact Receiver ESMC: radio monitoring from 0.5 MHz to

3000 MHz Compact Receiver ESMC

. Tools used: Matlab

Personal Strengths

. Can handle situations in a way that will not only please the

management but also be fair to the working team.

. Willing to learn, hardworking; accept challenges and work towards

the goal.

. Leadership qualities and at the same time believing in team work.

. Good time management abilities, Comprehensive problem solving and

Self-motivation.

Technical Exposure

. Programming Languages : Verilog HDL

. Frontend Synthesis Tools : Cadence RTL Compiler.

. Backend Synthesis Tools : Cadence SOC Encounter, Cadence ETS,

Cadence Virtuoso

. Scripting Languages : TCL

Personal Profile:

Father's Name : P.JanakiRamaiah

Mother's Name : P.Saraswathi

Sex : Female

Date of Birth : 22.09.1986

Nationality : Indian

Marital Status : Married

Languages Known : English, Telugu.

Hobbies : Singing, Reading Books

Permanent address : 8-6-1054, plot no.-132,Venkata ramana

colony,Vanasthalipuram, Hyderabad-

500070, Andhra Pradesh

Declaration:

I hereby declare that the above mentioned information is correct to

the best of my knowledge.

Date:

Yours Sincerely,

Place: Hyderabad.

(P.L.Sravanthi)

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