David Jacob

S/O Jacob Mathew,

#**, ***** *****, **** * Cross,

Aradhana Layout, Ejipura New Extension, Email Id: ace6u1@r.postjobfree.com

Bangalore-560047 Mobile No: +91-997*******

OBJECTIVE:

To obtain a job that will help me optimize my skills in the VLSI Industry along with contributing

extensively and efficiently to the organization.

ACADEMIC DETAILS:

• 8.4 CGPA in M.Tech [VLSI Design] from VIT University, Vellore [2011-13].

• 76.44% in B.E. [ECE] from M.V.Jayaraman College of Engineering, Bangalore [2007-11].

• 85% in 12th from Bishop Cotton Boys’ School, Bangalore.

• 79% in 10th from St. Joseph’s Boys’ High School, Bangalore.

SKILL SET:

• Languages: System Verilog, Verilog, C

• Tools Used: VCS, DFT Advisor, Fast Scan, Modelsim

• Areas of Interest: ASIC Design, Design For Test, RTL Design, Logic Design

CURRENT INTERNSHIP:

• Attending a 4 months internship cum training course at VERIFXN SOFTWARES PVT.

LTD. The topics being covered during the duration of the course are System Verilog and

Verification along with a Real Time Industry Mini Project.

M.TECH FINAL PROJECT DETAILS

Title: Study and Implementation of Fault Diagnosis Algorithms

Place: Indian Space Research Organization [ISRO], Bangalore.

Synopsis: Designed Fault diagnosis algorithms in C language to validate their functioning on

faulty circuits. Fault Suspects are generated from converted benchmark circuit netlists. The

suspects are either injected individually and simulated, or used in an encoding process, to obtain

the most probable fault locations in the given circuit. Scan Insertion is done using the DFT

Advisor/DC Tool and the necessary ATPG test vectors along with the fault coverage parameters

are generated for the circuits under test using the Fast Scan Tool.

M.TECH MINI PROJECT DETAILS

• An ASIC Design Based project on “Improvisation of Gabor Filter Using Verilog

HDL”, implemented using Encounter RTL Compiler tool.

• A FPGA Based Project “Implementation of a 16-bit Conditional Carry Select [CCS]

Adder Circuit for Low Voltage VLSI Implementation ”, implemented in Verilog on Altera

DE1 Board.

• A Testing Based Project on “Test Data Compression Using Dictionaries with Selective

Entries and Fixed Length Indices” implemented using Atalanta-M ATPG tool.

B.E. PROJECT DETAILS

Title: Beam Steering Electronics for a MEOLUT Phased Array Antenna.

Place: Indian Space Research Organization [ISRO], Bangalore.

PERSONAL DETAILS

Name : David Jacob

Father’s Name : Jacob Mathew

: 22nd December, 1987

Date of Birth

Nationality : Indian

Languages Known : English, Malayalam, Kannada, Hindi, Tamil and Telugu

Hobbies : Football, Basketball, Chess and Cricket.

ACHIEVEMENTS

• Elected Best House Captain for leading the House to The Best House Awards in

Academics, Sports and Games, Athletics and Football in the same academic year.

• Represented both School and College in Football and Dumb Charades and Won prizes.

Contact this candidate