Akshatha Karikal

**** ******** ****** *** * Los Angeles CA- 90007

Phone: 213-***-**** Email: ace2pw@r.postjobfree.com

LinkedIn Profile: www.linkedin.com/in/akshathakarikal/

Objective

Looking for a full-time position in VLSI Design, Computer Architecture, Digital Verification and Testing.

Education

Master of Science in Electrical Engineering May 2014

University of Southern California, Los Angeles, CA

Courses: MOS VLSI Circuit Design-I & II, Mathematical Foundations for Computer Aided Design, Computer

Systems Architecture, Computer Systems Organization, Digital System Design, Diagnosis and Design of

Reliable Digital Systems, Digital Image Processing

Bachelor of Engineering in Electronics & Communication June 2012

R.V College of Engineering, Bangalore, India

Skills

Languages: Verilog, VHDL, MATLAB, Assembly, C, C++, Perl.

Hardware: Xilinx Spartan-6, Pico-Blaze Soft Processor, Intel-8085, 8051, Panda-Board.

Tools: Synopsis Design Compiler and Prime Time, Xilinx - ISE, Chipscope Pro, PlanAhead, ModelSim.

Cadence Virtuoso – Layout GXL, Chip Assembly Router, Schematic L, ADE Spectre Simulator,

SimpleScalar, MATLAB, Eclipse IDE, OpenCV

Projects

Tomasulo Out-of-Order Processor - Implemented a 32-bit Tomasulo Processor with speculative

execution consisting of Copy Free Check Pointing, Issue unit, Load-Store Queue, Rotating Buffer,

Re-Order Buffer, Branch-Prediction-Buffer, Store Buffer, Store Address Buffer and Free Register List

modules. Aug 2013

5-stage in-order linear instruction pipeline - Implemented a 5 stage in-order linear pipeline with early

Dec 2012

branch design, Hazard Detection Unit, and Forwarding Unit in MIPS ISA using Verilog.

Chip Multi-Threading (CMT) - Implemented a single core multi-threaded in-order processor with an

Aug 2013

emulated non-blocking cache .

Aug 2013

Cache Coherency - Emulated MOESI Cache Coherency protocol for a 4-core processor.

Aug 2013

FIFOs - Implemented single clock FIFO and two clock FIFO using Block RAMs.

Special Calculator - Implemented a calculator with 4-way interleaving 256-bit SRAM, 6-bit multiplier,

24-bit dynamic adder and subtractor and a special MUX circuitry. Dec 2013

Digital Neuron and Neural Network - Designed a full custom standard-cell micro-library and optimized it

by transistor sizing and efficient layout design to minimize area-delay product of the neural network using

Dec 2012

TSMC 180nm library.

ATPG and Fault Simulation Algorithms - Implemented a Preprocessor, Automatic Test Pattern

Generator using D-algorithm and PODEM algorithm, and Fault Simulator using Parallel Fault Simulation

Dec 2013

and Deductive Fault Simulation.

Processor Design - Explored design space of a typical micro architecture enhancement to an existing

May 2013

processor design to increase the MIPS rating.

Image Processing - Performed Image manipulation, enhancement & noise removal, Morphological

Processing, Digital Half-toning, Spatial Warping, Texture Analysis & Segmentation, Optical Character

Dec 2013

Recognition, Face Morphing on several test images.

Remote Surveillance AutoBot - Implemented a robotic control system for video surveillance by creating

an ad-hoc network confined to the PandaBoard and the remote laptop using the Robotic Operating System

(ROS) with face detection and feature extraction. May 2012

Medical Database Management System - Designed a Database with GUI developed in C programming

language which holds the record of patients and the medicine that was prescribed to them. May 2011

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