RESUME

SHAIK.FIROZ BASHA

Email:acduis@r.postjobfree.com

Mobile: +91-990*******

CAREER OBJECTIVE :

Seeking a challenging career to take part in the growth of the

industry with my ability and technical skills, which will contribute to the

organization growth.

ACADEMIC PROFILE :

> B.Tech in ECE from SAFA College of engineering & technology, JNTU

UNIVERSITY with 61.40 % in 2010.

> Intermediate in M.P.C from Basi Reddy junior college, A.P State Board

of Intermediate Education with 76.40% in 2006.

> S.S.C. from Z.P.H.S Prathakota, A.P Board of secondary Education with

79.80% in 2004.

WORK EXPERIENCE :

Organization :MALLA REDDY INSTITUTE OF ENGG & TECH.

Designation :LAB.ASSISTANT (ECE Dept.)

Period : From 19 July, 2010 to 28 Nov, 2013 (3 Yrs 4

months).

Responsibilities:

. Carried out practical sessions with explanation about the purpose of

the experiment and the procedures that follow to seek results.

. Also did a network administration ( systems formatting and software

installations,LAN/WAN installation ),

labs handled:

. Micro Processor and Interfacing Lab.

. Electronic Devices and Circuits Lab.

. Simulation Lab.

.

TECHNICAL SKILLS :

Languages : C, VHDL and MPI lab.

Assembly languages : 8086 microprocessor, 8051 microcontroller.

Operating systems : Windows XP, UNIX

Packages : Ms office,

Specialized : Hardware & Networking.

PERSONAL SKILLS :

. Capable to overcome any kind of problem

. Self confidence, positive thinking and self motivated.

. Good communication skills.

PROJECT PROFILE:

Project Title : 128-bit Modified Area Efficient Carry

Select Adder.

Duration : 4 Months.

Implementation Language : Verilog-HDL.

Description :

As we know that the carry Select Adder (CSLA) which provides one of the

fastest adding performance. And while we observe the structure of carry

select adder, one thing is clear that there is a scope for reducing the

area and power consumption in the carry Select Adder. Recently a new CSLA

adder has been proposed which performs fast addition, while maintaining low

power consumption and less area. This work mainly focuses on implementing

the 128 bit low power consumption and less area required carry select adder

by modifying the architecture.This work evaluates the performance of the

proposed designs in terms of delay, area, and power. The results analysis

shows that the proposed CSLA architecture is better than the regular SQRT

CSLA. The proposed design has been developed using verilog HDL. synthesized

and simulated using Xilinx ISE Simulator and verification is done using

modelsim.

PERSONAL PROFILE:

Fathers name : S. MAHABOOB BASHA

Date of Birth : 06-03-1989

Nationality : Indian

Gender : Male

Languages Known : Hindi, English, Telugu,Urdu.

Permanent Address : Prathakota (v),

Pagidyala(m),

Kurnool (d)

Andhra Pradesh-518412

DECLARATION

I here by declare that the information furnished

above is true to the best of my knowledge.

S.FIROZ BASHA

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