TERESSA Lovette L. ANGLINMATUMONA

Rochester, NY *4610

585-***-****) or 510-***-****

acduc7@r.postjobfree.com

PROFESSIONAL

OBJECTIVE: A position as a Senior Staff Process Engineer/Scientist which

will effectively utilize extensive knowledge of

Semiconductors, Oxide Etch Processes, Polymeric Materials,

Evaluate Chemical Data and Statistical Analysis in an

atmosphere conducive to professional growth and

development; motivated by challenge and diversity.

EDUCATION:

SAN JOSE STATE UNIVERSITY, San Jose, CA

M.S., Chemical Engineering Graduated: May 2005

* Worked Full-Time as Process Engineer Concentration:

Semiconductors (plasma etch applications)

Thesis Project: Characterization and Optimization of a New Gas

Chemistry to Reduce ARDE for High ASPECT

Ratio Via Etch Process in a High Density ICP System

NORTH CAROLINA STATE UNIVERSITY, Raleigh, NC

B.S., Chemical Engineering and B.S., Applied Statistics

Graduated: May 1999

Completed: NCSU Development Leadership Series

AREAS OF

EXPERTISE: Background includes special classes and/or experience in:

( Design of Experiments (DOE/ANOVA) ( JMP( &

Mintab( Statistical Software

( Statistical Process Control (SPC) ( Residential

Expert SEM & Defect Analysis/Plasma Etch

( Process Integration Requirements (

Vendor/Customer Relations

( Departmental Liaisons ( Engineering Alliance

( Guest Lecturer;: Design of Experiments (DOE) at SJSU

AFFILIATIONS: American Vacuum Society (AVS)

Poster Presentation at AVS 52nd International Symposium, Boston,

MA, October (2005). Paper Title: Characterization

Methodologies for Unsaturated 1,3-C4F6 Plasma used to

Investigate Aspect Ratio Dependent Etch and Etch Characteristics

with Comparison to Saturated c-C4F8. 2) Invited Talk at NCCAVS

PEUG User Groups, Sunnyvale, CA, May (2006) Subject: The

Transition from Saturated (c-C4F8) to Unsaturated (1,3-

C4F6)Perfluorocarbons: Effects on Selectivity and ARDE in Via-

hole Plasma Etch Applications. 3) Poster Presentation at AVS

53rd International Symposium, San Francisco, CA, October (2006).

Paper Title: Plasma Chemistries for High-Aspect-Ratio

Dielectric Etching Beyond 65 nm Node.

Certifications: SAS JMP ANOVA/DOE/Regression Analysis (Completed. SAS

Institute; San Jose, CA); Lean Six Sigma -White Belt (Aveta Business

Institute), Yellow Belt:in process, Greenbelt/Black Belt/Project

Management: in process (Expertrating).

Core Responsibilities:

. Applied statistical methods (ANOVA/DOE etc and performed

mathematical calculation to determine process capabilities (Cpk/SPC

etc and process improvements.

. Established process and equipment specification for new product

introduction (NPI) and new equipment in compliance with industry

standards. Conducted process and equipment acceptance tests for HV

manufacturing.

. Determined appropriated spec limits and critical process variables for

plasma etch process specifications using statistical analysis systems

such as minitab and JMP.

. Coordinated and created excursion prevention techniques to resolve

quality problems or excursion prevention. Recommended and implemented

changes and improved modifications that reduced cost.

. Performed research and development of new materials; plasma gases;

plasma etchers for dielectric plasma applications beyond 130 nm node

(45 nm) for semiconductor technologies. Compiled statistical data

reports.

. Investigated and developed polymeric materials of fluorocarbon

chemistry mixtures for semiconductor BEOL plasma etch processes for

breakthrough improvements in etch selectivity; ARDE; microloading and

dimensional control for integrated products. Compared legacy recipes

to new optimized recipes for bench mark performance.

. Used process maps, design of experiments (DOE), and data analysis

techniques to establish critical parameters and tolerance ranges for

new products and manufacturing processes with summary report.

Additional Job Duties Include:

?Cross-training and process development for dielectric etch of

all TEL Unity; TEL DRM;TEL SCCM; and AMAT

plasma etch equipment platforms for Logic; NOR; NAND; and DRAM

technologies.

?Provided relevant support to internal and external customer

relations for coordination of new equipment qualifications

and process certifications for dielectric etch applications.

?Developed and characterized processes compatible with advance

plasma etch techniques for dielectric technical platforms.

Created and advanced processes to deliver optimal plasma etch

characteristics based on the industry specification.

?Able to provide knowledge of dielectric plasma etch techniques

and effective troubleshooting skills to solve process problems.

?Experienced with new plasma chemistry and equipment selections;

including qualification; installation; and transfer.

?Experienced process ownership includes STI Nitride; Self-

Aligning-Contact; Spacer,Via (Dual Damascene);& PHM

Applications.

TERESSA Lovette L. ANGLINMATUMONA Page 2

CAN-AM Consultants (Kodak), Rochester, NY, Senior Process

Engineer; 10/03/2011-12/08/2011

?Owned PVD Process Characterization and Optimization for W/WN-

W/ALSI/ITO Metal Film layers.

?Conducted PVD chamber characterization as a function of gas

flows, chamber temp, DC power and gap position to

investigated the impact on uniformity, resistivity, film

thickness and CALFACTOR.

?Design and conduct design-of-experiments (DOE) and provide

recommendation for process improvements.

Nuvotronics, LLC, Blacksburg VA (Start-up Company), 6/2008 to

1/2009)

Sr. Process Development Engineer (MEMs Product Development),

Tenure: 12/2/2008 to 1/8/2009

?Worked with Product Lines to understand their specific product

roadmap requirements and use as input for MEM

Platform road-mapping.

?Developed & Implemented Statistical Process Control Database

Systems across all fab modules.

?Team player with a strong sense of urgency to meet product

requirements on schedule.

Micron Technology, Manassas, VA; Contributions;: Process Owner for all

TEL DRM Dielectric Etch Applications.

Process Module Owner (Dielectric Etch Applications), Tenure:

8/2006 to 2/2008

?Led and developed process characterization experiments for low-k self-

aligning-contact (SAC) for DRAM 45 nm node.

?Designed, conducted, executed and analyzed experiments such as

response surface, screening, and split plots;

influencing the selection of plasma chemistry. Set-up

Statistical Analysis and SPC for new products and new tools.

?Conducted SWR experiments to investigate causes of process

variation and developed new processes to increase

product yield with improved process margin for wafer

fabrication.

?Led and coordinated new tool install qualifications, NPI, and

product qualification and release for fab ramp and continuous

improvements; and interacted productively with a diverse team

sharing these goals.

Intel Corporation, Rio Rancho, NM & Santa Clara, CA

Co-Develop/Process Transfer Engineer, Tenure: 3/2004 to 8/2006

?Dry Etch Team Leader for tool downs and fab excursion/SWATS impacting

yield performance.

?Led, developed, conducted SWR experiments for dielectric etch process.

New descum step led to a 30% improvement to inline defects for 32 nm node

flash memory dielectric application and yield improvements.

?Evaluated tool capability, tool mismatches relative to the golden

tool; & process performance for different plasma etcher platforms;

based on inline metrics & end-of-the-line parametric data.

?Transferred processes from R&D to HVM production; including

recipe development and modification.

?Analyzed process issues/tool qualifications, identified root

causes and provide probable solutions to prevent reoccurrences.

Advance Micro Devices (Submicron Development Center), Sunnyvale, CA

Process Engineer, Tenure: 5/1999 to 4/2003

?Investigated,developed and implemented "new plasma chemistry" for high-

aspect-ratio devices for 130 nm node technology that led to a 2 to 1

improvement in selectivity; ARDE & dimensional control.

?Managed time-line and cost in reducing particles in only two months; Total

cost to restore solvent tool at .15 um detection level using SP1 was $4,500

with a savings of $10K. Optimized wet clean process for BEOL resulting in

a 48% yield increase for 4 Mb and 29.2% for 1 Mb.

Developed: ?Developed AMD 1st-ever Bare Wafer Inspection Methodology Using

Orbot Coordinates.

New methodology enabled cheaper; and faster studies of

defects.

?Developed FSI Temperature methodologies to test cleaning

efficiency using APM chemistry.

New methodology led to improved cleaning efficiency using

APM chemistry.

? Developed cleaning efficiency methodology for FSI system.

Developed 1st contact clean process; recipe

was considered for a standard across all AMD fabs.

FUJITSU Network Communications, INC., Raleigh, NC

Quality Assurance Intern, Tenure: 5/1998 to 1/1999

? Utilized SAS( programming for bandwidth communication products

to develop regression model and statistical templates to perform

descriptive statistics on software code parameters; instrumental in ISO

9000 audit.

DUPONT Chemicals Company, Wilmington, DE

Process Development CO-OP, Tenure: 12/1992 to 12/1993

?Performed experiments on a laboratory scale "Breadboard Refrigeration

System" to quantify refrigerant characteristics; subsequently co-authored

technical paper on the subject. Supervised technician and trained team

members.

XEROX Corporation, Webster, NY (XCEL Program)

Process Development Intern, Tenure: Summer, 1989-1992

?Conducted pilot scale studies for toner extrusion

processes.

?Developed operating procedures for new dryer process

and trained technicians.

REFERENCES: Excellent Professional and Personal References Available

Upon Request.

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