Prasad G Gaitonde
HOME: **** ********* **
Irving, TX 75063
214-***-**** (m)
acdrj9@r.postjobfree.com
SUMMARY
. combination of robust Microelectronics / Electrical engineering
knowledge together with leadership in problem solving, process
improvement and execution by following deep technical understanding
and business ethics - earned through 11 years work experience (9 yrs.
in semiconductor industry), intense academic study (was outstanding
grad student '04), excellent track record, and through project team
involvement.
. Demonstrated the ability to handle rapid learning curves, multi-
tasking environments, and timeline pressures
. Good team player, flexible, & sincere. Detail-oriented, a fast learner
and go extra mile to get the job done
. Expertise includes ESD/Latchup and circuit design
. Authorized to work for any employer in USA
EXPERIENCE
Texas Instruments, Dallas, TX
08/10 - Present
CMOS Development Engineer, Member of Technical Staff
. Execute the design in CMOS (TI) and Foundry processes on nodes 90nm,
45nm, 28nm and 20nm.
o Experience working closely with process integrators, or
manufacturing engineers.
o Experience working in Manufacturing environment, yield
improvement, and Quality.
. Failure analysis troubleshoot and mitigation for fixing production
level issues.
o Six Sigma tools to identify root cause and develop corrective
actions for failure modes identified through failure analysis.
Green belt training underway.
o Kaizen, Continuous improvement, FMEA, RCCA followed.
. Development of ESD structures,
o for ASIC/SoC - Railclamp and Dual diodes, snapback, IEC for
applications such as USB, HDMI, GPIOs, DDRx, SDIO, serdes, LDO
and power switching applications.
o Owned active clamp (TEXFET) development; patent pending on a
novel clamp design. Placement and layout expertise.
o Test structure development. General testchip and test structure
development, layout, DRC. DOE.
o TLP lab management, process improvement and wafer probe TLP
testing.
o Working knowledge of automated testing techniques. Validation of
structures.
o Creating and auditing ESD Rule document and spec documents for
checkers. Quantify value in amendments and fix issues.
. Generating whitepapers or PowerPoint presentations (or
training docs) for customers.
. Automated DRC and pattern/extract ESD and Latch up checker
development.
o Automated ESD checker Nucleus project management for last 2
years.
. PERC training completed.
. PMP training certification underway.
o Competitor benchmarking for wireless, consumer and connectivity
system-on-chip.
o ESD review and provide design change recommendations for JEDEC
and Q100, automotive.
. Analog Design:
o Single-stage and Two-stage OPAMP designs as part for a LDO
design.
o Low 12ppm/C temperature coefficient, low power, trimmed brokaw
band gap design.
o High (>=60DB) PSRR, low quiescent <15uA current short circuit
protected LDO Regulator with 15ppm/C temperature coeff. 10mA
nominal load current and >=90% efficiency In Texas instrument's
in-house technology.
Maxim Integrated Products, Sunnyvale, CA
09/05 - 05/10
Tech Research & Development, Member of Technical Staff (05/07 - 05/10)
. Understanding of and Worked on Analog BiCMOS 0.2?m Si/SiGe
Bulk/SOI/BCD Maxim ESD
. Owner of HV (110V) high-frequency SOI (SiGe) BiCMOS process ESD
development for Multimedia BU
. Studied Maxim's SOI development. Developed I.O.S test-chips and
scribeline
o PT test development
. Developed ESD Cells such as diodes, SCRs, LV (5V/14V) MOS, HV (upto
65V) MOS, and MOS/BJT active & passive clamps, IEC / AEC compliant
cells, and Primitives for ESD Library (PDK)
. Hspice simulation for Active clamps - CMOS and biCMOS based clamps,
DualDiode and Railclamp architecture
. Setting up decks, running simulations, and validating clamps against
TLP data
. Custom ESD development for Diff Opamps, Power regulators, Hot-swap,
low cap, high speed IO, positive/negative protection with 100%
success, chips into mass production
. Set up CDM simulation methodology. Responsible for generating white
papers
. Developed ESD Design and Latch-up Rules, Designer's Guidelines to ESD
(Cookbook)
o Reviewed designs/layouts
. Failure Analysis on power management and multimedia products,
providing solutions and managing the project
ESD & Modeling Group, Associate Member of Technical Staff (09/05 - 05/07)
. Contributed to 0.8, 0.4 & 0.2 um Maxim BiCMOS process, TSMC 0.35 &
0.18 process development
. Set up testplan, and Design of Experiment. Characterized Silicon using
Transmission Line Pulsing (Home grown, or Thermo Fisher/ Oryx -TLP),
MK2 HBM/MM, and DC hot/cold using 4156
o Chip Qualification using JEDEC/Mil HBM standard
. Designed ESD Cells such as IEC compliant cells, MOS, lnpn/ lpnp and v-
BJT clamps
. Automatic schematic level program development & implementation on
netlist level (in HSPICE & Cadence) - Rule-based program that flags
violations & suggests circuit improvements
o Rules are process dependent
. Regression testsuite for Auto ESD checker, testing and release to
designers
. Developed I.O.S test-pattern drop-ins and test-chips by design of
experiment, layout and verification
. Created ESD Library (PDK) & design guides for Automotive/ SSIP/ SPC/
SPM/ Mutimedia Bus
. ESD Failure Analysis - Fault isolation, Fault location & Analysis.
Recommendation to fix IC/Chip for customers
Intersil Corp, Palm Bay, FL 05/04
- 05/05
TCAD Intern, CAE / ESD / Modeling Group
. Developed NMOS ESD protection clamp SPICE Models and set-up simulation
methodology for snapback ESD-Clamp Design. Published thesis and paper
. Contributed to Electrostatic Discharge Protection Methods & Techniques
for Intersil's, power management integrated circuits and system
. Extracted lnpn parameters using Silvaco TCAD Process Simulator Athena
and Device Simulator Atlas
o Developed NMOS (lnpn) model using Verilog A
. Predictive Trigger Voltage simulation of NMOS ESD protection clamp -
NMOS and parasitic BJT Turn-On voltages
Florida Tech, Melbourne, FL 05/03
- 05/04
Research Assistant, Electrical Engr. Department
. Literature search on HgCdTe (MCT) semiconductor, Infra-red detectors,
and material processes for the fabrication of integrated monolithic
multicolor HgCdTe IR Focal Plane Arrays
. Mobility & Lifetime study of HgCdTe (MCT) Infrared Detector compound
semiconductor material
. Addressed combinations model of material from MWIR (3-6.5 microns) up
to VLWIR (>14 microns) in two to as many as four layers
EDUCATION:
. Master of Science (MS, Honors) in Electrical Engineering from Florida
Institute of Technology with GPA of 3.88 out of 4.00. Specialized in
Microelectronics. Thesis on 5V ESD clamp Modeling & Simulation.
Graduated May 2005.
. Bachelor's in Electrical Engineering, specialization in Power systems,
controls, and Circuit design.
OTHER PROJECTS
Analog IC Design:
. Detailed design analysis of Intersil Opamp HA-2600, Detailed analysis
of TI's OPA735 family
o Completed Analog and Mixed signal Circuit Bootcamp by Prof.
Philip Allen
Digital Signal Processing:
. Filtering 'annoying' tones from audio signal using MATLAB. The tones
are sinusoids of frequency 701.17 Hz and 3.1 kHz, mixed with a movie
sound clip sampled at frequency 22.05 kHz
o The clip was 8 bit, and its length is 1,010,882 samples
o Filtered out the unwanted frequencies, written to a file
'speech06_filtered.wav', filter length was 80
VLSI Processing:
. Developed BiCMOS SOI process flow for VLSI class
o Analyzed and reported Silicon on Insulator process with LOCOS,
deep-trench, and 2 Metals in 36 process steps
o Analyzed processing costs
Fabrication Lab:
. Hands-on fabricated CMOS and Well resistors using 6um 4inch FL tech
facilities
o Tested and analyzed devices
o Wrote report
o Recommended yield improvements
PUBLICATIONS & PATENTS
. A patent pending on 'Level Triggered ESD Active Clamp for Fast rise
time Power'. 2013-14
. A thesis on 'Predictive Trigger Voltage Simulation of NMOS ESD
Protection Clamp', Prasad G Gaitonde, Florida Institute of technology,
May 2005
. 'Predictive Design Of ESD NMOS protection clamp for parasitic BJT
Trigger', P. G. Gaitonde, S. J. Gaul, T L Crandell, S K Earles, IEEE
International Integrated Reliability Workshop (IIRW), 2005
TOOLSETS:
. Proficient in Cadence Analog and Mixed signal IC Circuit Simulation,
Completed Certification Coursework
. at Cadence, Inc. Schematic composer. Used day to day, CDB, clear case,
DS, and OA database. Simulations using Spectre, PSPICE, and hspice in
View logic
. Layout Tools - LTL, Virtuoso, cadence k2 and Ledit. PCB/PWB layout
. Physical verification - Calibre/Hercules/Assura DRC & LVS.
. Programming Languages - completed coursework in Perl, C/C++
certification, MATLAB, VB, Splus (S+), shell scripts,
. Unix Scripts. Completed coursework in Verilog and VHDL, design
verification.
. TCAD Tools -SILVACO (athena/ atlas), Ise-TCAD, SUPREM, Synopses.
. OS - Windows, Red-Hat/Suse Linux, Sun-Solaris, HP UNIX.
. Proficiency with MS Office, Excel, Outlook and Visio.