MURALI KANCHAM

E-mail: acdpxj@r.postjobfree.com Mobile No: ( +91-906*******

Career Objective:

Seeking a position to utilize my skills and abilities in the VLSI

Design field that offers professional growth while being resourceful,

innovative and flexible.

Professional skills:

. Well knowledge of PHYSICAL DESIGN flow in Floor planning, Power

planning, Placement, Clock Tree Synthesis(CTS), Routing,Static

Timing Analysis(STA), IR Drop Analysis and Crosstalk.

. Good knowledge of Digital Design Concepts.

. Good knowldge of CMOS Fundamentals.

. Effective knowledge of Floor planning, Placement and Static Timing

Analysis(STA).

. Basic knowledge in PERL, TCL, C shell scripting.

. Hands on experience on Physical Design Tool of Synopsys IC Compiler

and Cadence First Enconter.

. Comfortable with windows, Linux operating systems.

Academic Qualifications:

. B. Tech (Electronics and communication ) from Avanthi inst of

Engineering Technology, JNTU, Hyderabad in 2012 with 77%.

. Intermediate from J.C.N.R.M. Junior College, Tadpatri in 2008 with

88%.

. SSC from MPL Boys High School, Tadpatri in 2006 with 82%.

Professional Training:

. Post Graduation Diploma in VLSI Physical Design from Shastra Micro

Systems, Hyderabad.

Tools: Synopsys - (IC Compiler), Cadence -(First Encounter).

Related course work: ASIC Design Flow, Concepts of Advanced Digital

Design, Basic CMOS Fundamentals, ASIC Physical implementation flow -

Floorplan, Placement, Clock Tree Synthesis, Routing, Static Timing

Analysis, Sign-off Analysis (DRC, ERC, LVS), Fundamentals of Linux and

Scripting Languages (C-Shell, PERL & TCL).

Technical project:

Title : Physical Design Implementation of DTMF

Chip using

180nm Technology.

Tool Used : First Encounter (Cadence)

Metal Layers : 6

Instance Count : 6k

Net Count : 200k

Clock Frequency : 300MHz

Roles and Responsibilities : To Perform Floor Plan and Power Plan,

Placement, Clock

Tree Synthesis, Routing and Static Timing

Analysis(STA).

Issues Resolved : Resolving Timing, Congestion and IR- Drop Analysis

and

Electro Migration Issues in all stages of

the design.

Academic project:

TITLE: Generic Lossless Visible Watermarking

The main aim of the project is capability of lossless image recovery

is proposed. The advance of computer technologies and the proliferation of

the internet have made reproduction and distribution of digital information

easier than ever before. Copy right protection of intellectual properties

has therefore, become an important topic. By using watermarking we can

provide the copy right protection .

Domain : DSP(Digital Signal Processing)

Team size : 3

position : Team Leader

Personal Details:

Name : Murali kancham

Father's name : Chalapathi kancham

Sex : Male.

Date of birth : 15th June 1991

Permanent address : G3-Lillies, Pavani Residency,

Puttanahalli, Yelahanka,

Bangalore-560063.

Declaration:

I hereby declare that the above furnished information is true and

correct to the best of my knowledge.

Place:

Date: (Murali Kancham)

Contact this candidate