USHA RAGHURAM, Ph.D. Email: acdpds@r.postjobfree.com

***** *** ****** ***** 408-***-**** (h)

Saratoga, CA 95070 408-***-**** (c)

SUMMARY:

Assembled and managed teams of engineers for semiconductor process development, integration and transfer to

manufacturing site/foundry and customer support.

Managed projects to implement statistical process control, cost analysis, productivity and yield improvements that

resulted in better efficiency and significant cost savings.

Closely and effectively worked with internal and cross-functional teams while acting as an intermediary between

foundry and tool suppliers. This was crucial in resolving technical as well as logistic hurdles in delivering

products on time.

Have taken processes and technologies from concept to high volume manufacturing.

Extensive knowledge and hands-on experience in semiconductor and MEMS process/technology development,

process integration and transfer to foundry.

Experienced in working with R&D fabs (SNF, Berkeley, SVTC) as well as foundries (TSMC, Toshiba).

Established methodologies and organized technology specs and transfer documents.

EXPERIENCE:

Rambus, Inc. 2012 to date

Senior Principal Engineer

Led process/ integration activities for embedded RRAM applications that delivered two test chips in less than a

year and enabled evaluation of cell improvements, design solutions and programming algorithm optimizations.

Achieved the goal of making RRAM devices with fab friendly materials and good on/off ratio, retention and

endurance.

Developed process flow & processes, resolved integration issues, and evaluated new materials and delivered

reproducible devices with good yield.

Worked with mask vendors, foundry and design teams to ensure seamless litho processing between different

steppers at different sites.

Spearheaded Ebeam lithography work and delivered devices that proved extendibility of RRAM technology to

sub 45nm technology nodes.

Intermolecular Inc., San Jose, CA 2011 to 2012

Senior Member of Technical Staff

Developed and integrated processes and work flows to effectively evaluate and identify new materials.

Led teams that evaluated materials using combinatorial methods for replacement metal gate and Cu barrier

modules for 20 and 14nm technology nodes.

Identified, enabled, and managed external resources for processing and analysis across programs.

Managed CapEx requirements, identified and procured new equipment and set them up.

Stanford Nanofabrication Facility, Stanford, CA /

Aerospace Missions Corporation, El Paso, TX 2009 to 2011

Consultant at SNF / Principal Nanotechnology Engineer at Aerospace

Single-handedly did the process design, development and integration of a novel Fabry-Perot optical filter and

detector array for a DoD project - executed all steps from mask design to packaging.

Part of expert 4-person team that delivered a camera with hyper-spectral detection capability for UAV.

Designed and developed processes for ICs, MEMS processing.

Designed and processed inter-digitated electrode devices on glass substrates with micron level geometries

including a passivation scheme for withstanding acidic environment.

SanDisk Corporation, Milpitas, CA 2002-2008

Matrix Semiconductor, Santa Clara, CA

Process Engineering Manager/Principal Engineer (2007-2008)

Member Technical Staff/ Sr. Staff Process Engineer (2002-2006)

Led a team for successful development and integration of modules for 28nm 3D memory technology using double

patterning techniques.

Spearheaded on-time transfer of 80nm 3D technology to yielding products in foundry (TSMC).

Developed key etch modules with good process margin to enable the unique 3D technology transition from 250

nm to sub 30nm both at the R&D and foundry sites.

Directed the resolution of multiple key integration issues in the development/transfer phase which led to yielding

products/higher yield for the 3D technology.

Supertex, San Jose, CA 2000-2002

Etch Section Head

Assembled and led a team of etch engineers to develop customized processes for ICs and MEMS customers.

Improved overall productivity through drastic reduction of problem and scrap lots by over 75%.

Promoted systematic root cause analysis by facilitating team work between process and maintenance groups.

This resulted in quick problem resolution and improved yields.

Streamlined and updated specs; implemented processes to meet customer specifications.

Cypress Semiconductor, San Jose, CA 1995-2000

Principal Process Engineer (2000)

Staff Process Engineer (1997-2000)

Senior Process Engineer (1995-1996)

Developed and implemented robust, manufacturing-ready etch processes for 0.5 to 0.15 micron technology nodes

with focus on reproducibility and process margin in R&D and manufacturing fabs.

Pioneered the development and implementation of the self-aligned contact etch process with resist masking for

high-volume manufacturing.

Improved equipment productivity with an emphasis on defect reduction through implementations of monitors,

statistical controls, troubleshooting flow charts, and proactive preventive measures.

Responsible for training and mentoring new hires and engineers across sites on new technologies.

Paradigm Technology, San Jose, CA 1993-1995

Process Engineer

Worked as the sole sustaining engineer for the etch area: responsible for all plasma etch, strip and clean processes

for 0.5 –1 micron SRAM products.

Promoted team work between equipment and process technicians and engineers and implemented the required

tool/process controls to minimize in-line scraps and problem lots and improve yield.

PATENTS, PUBLICATIONS, AND PRESENTATIONS:

20+ published US patents in semiconductor processing /integration; 15+ publications & presentations

EDUCATION:

Ph.D., Organic Chemistry, Indian Institute of Science, Bangalore, India

M.S., Materials Engineering, San Jose State University, San Jose, CA

M.Sc., Physical Chemistry, University of Madras, Madras, India

MEMBERSHIPS: American Vacuum Society and Electrochemical Society

LinkedIn Profile: http://www.linkedin.com/in/usharaghuram

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