PRIYA SINGH

M.Tech VLSI & Embedded Systems

Objective:

To be an integral part of a respected and professional organization, where

I can enhance myself in the field of FPGA, VLSI and ASIC and keep myself

updated with the cutting edge technologies.

PERSONAL DETAILS

Name: Priya Singh

Date Of Birth: 15/04/1990

Father's Name: Pritam Singh

Address : Qtr No: P 100, Jal Vayu Vihar, Sector 29

Faridabad, Haryana 121008

Contact Number: 91-901*******

acdjki@r.postjobfree.com

Email:

ACADEMIC RECORDS

EDUCATIONAL QUALIFICATION

Degree Institute/Univers Period Percentage

ity

From To

M.Tech ( VLSI and Manavrachna JULY 2012 MAY/JUNE 2014 9.22(CGPA)

EMBEDDED SYSTEMS ) international

university

B.E (ELECTRICAL Goa College Of JULY 2007 MAY/JUNE 2011 66

and ELECTRONICS) Engineering (Goa

university)

H.S.S.C Kendriya JUNE 2006 MARCH 2007 79

vidyalaya no. 1

Vasco-da-gama

(CBSE Board)

S.S.C Kendriya JUNE 2004 MARCH 2005 77.4

vidyalaya no. 1

Vasco-da-gama(CBS

E Board)

TECHNICAL SKILLS

Methodology UVM

Hardware design languages (HDL) VHDL, Verilog HDL

Hardware verification languages (HVL) System Verilog

Tools (design, simulation) Spyglass, design compiler(dc shell), PSPICE,

TSPICE,HSPICE, Xilinx ise, Cadence tools

experience (Incisive Simulator, Incisive

Formal Verification, Incisive Enterprise

Manager).

Operating System Unix, Windows

Familiar Bus System AMBA (AHB, ASB, APB), IPS

Programming languages C, C++

EXPERIENCE

ST Micro electronics Pvt. Ltd.

July 2013 - Jan 2014

. ST is among the world leaders in a broad range of segments, including

semiconductors for industrial applications, inkjet printheads, MEMS

(Micro-Electro-Mechanical Systems), MPEG decoders and smartcard chips,

automotive integrated circuits, computer peripherals, and chips for

wireless and mobile applications.

. Designation:- Project Trainee (In Automotive Product Group)

> Project undertaken INTEGRATION VERIFICATION OF MEMU IP IN VELVETY

SoC .

> Responsible for uVM based testbench development and verfication of

MEMU IP in Velvety SoC, developing testcases, debugging testcases.

> Running the regression suite, maintenance of SoC testbench,

publishing the regression results, coverage data.

ACADEMIC PROJECT

B.E Final Year Project

Kinetic Energy Recovery System

Kinetic Energy Recovery System(KERS) deals with the conversion of energy in

vehicles,which is able to reduce fuel consumption by certain amount(say

20% approx) . KERS is a hybrid device that is set to revolutionize vehicles

with environmentally friendly, road relevant, cutting edge technology. KERS

is an energy saving device fitted to the engines to convert some of the

waste energy produced during braking into more useful form of energy.

M.Tech III Sem Project

Design and Synthesis of UART protocol using Verilog HDL

Developed a Verilog based UART (Universal Asynchronous Receiver and

Transmitter), and demonstrate its working (as both transmitter and

receiver) by interfacing it to SkyBlue-Line interface. Designing was

carried out using FSM methodology and later synthesized using synopsis

design compiler .

ACHIEVEMENTS / ADDITIONAL INFORMATION

Competitions:

Received Merit certificate and stood 7th in 1st nation wide Bio-technology

Olympiad.

Participated in Paper Presentation held by SPARX 2011.

Participated in an orientation programme on mountaineering by EXPLORE

HIMALAYAS at Himachal Pradesh .

Strengths : Sincerity, punctuality, never say die spirit, leadership

skills, good communication skills along with confidence, good social

abilities and my down to earth nature.

Hobbies / Interests: Listening to music, surfing the net, Networking and

cooking, solving puzzles, travelling, singing.

Declaration -

I hereby affirm that the information given in this application blank is

true to the best of my knowledge.

DATE:

SIGNATURE :

PRIYA SINGH

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