curriculum-vitae

Bal Raj Kurva Contact:

acdjdq@r.postjobfree.com

M.Tech (NIT, Jalandhar) Phone: +91

963-***-****(Official)

B.Tech (JNTU, HYD)

Statement of Purpose:-

To obtain a challenging position as a Verification Engineer and strive

for excellence with dedication, proactive approach, positive attitude and

passion towards the work that will fully utilize my logical, technical and

reasoning abilities in the best possible way for the fulfillment of

personal and organizational goals.

Professional Experience:-

1. Around 2.10 years of professional experience in the field of VLSI

Design as ASIC Verification Engineer.

2. Currently working with Kacper Technologies Pvt. Ltd as an ASIC

Verification Engineer from (June 2012 to till date).

3. Worked as a RTL Design Engineer with Kacper Technologies Pvt. Ltd.

from (June-2009 to July-2010).

Summary Of Qualification:-

> Experience in writing RTL models in Verilog HDL and Test benches in

System Verilog.

> Very good knowledge in verification methodologies OVM and UVM.

> Experience in using industry standard EDA tools for the front-end

design and verification.

> Good Experience in writing coverage scenarios and coverage groups.

Educational Background:-

> 2010 - 2012:- M.Tech in VLSI Design at Dr.B.R.Ambedkar National

Institute of Technology (NIT) Jalandhar with C.G.P.A of 7.25 on a 10

point scale.

> 2005 - 2009:- B.Tech in Electronics & Communication Engineering at

JNTU, Hyderabad with an aggregate of 60.37% of marks.

> 2003- 2005:- Intermediate (Mathematics, Physics, Chemistry) 88.10%.

> 2003:- 10th class (S.S.C) examinations conducted by State Board of

Andhra Pradesh and secured 70%.

Projects:-

> Development of Verification IP for PCIe Gen 3 (Transmitter) (Jun 2013 to

Till now)

Tool used : QuestaSim 10.1

HVL used : SystemVerilog with OVM

Role and Responsibilities:

. To understand the specification of PCIe Gen 3 (Transmitter)

Protocol.

. Adding test scenarios to the DL, coding of DL checker and

debugging of this DL Functional test cases and reporting any

bugs if found.

. Responsible for Data Link layer (DL), Writing Different

constraints for DL.

. Responsible for development of different corner test cases.

> Development of Verification IP for AMBA AXI-4 Master (Jun 2012 to May

2013)

Tool used : QuestaSim 10.1

HVL used : SystemVerilog with OVM

Role and Responsibilities:

. To understand the specification of AMBA AXI-4 Master bus

protocol.

. Developing the Verification Architecture for AMBA AXI-4 Master

bus protocol and Development of Coverage model for master

environment

> Design of a High Performance Reconfigurable FIR Filter using Audio

Application (Jun 2009 to July 2010)

HDL used : Verilog Design and Vitex-2 FPGA

Verification

Tool used : Xilinx ISE-13.2

Role and Responsibilities: The Emergence of wireless and wire line digital

communication has advanced exponentially in recent years. The main object

of in this thesis is design and implementation of FIR Filter Architecture

which keeps in account of re-configurability and also focus is on to

improve the three quality of a digital factors using Different type of

multiplier to compare the power consumption, area and speed. In this

design, I have considered the Audio speech record coefficients.

Technical Strengths:-

Operating system : Linux, Microsoft Windows

Hardware Description Language : Verilog

Hardware Verification Language : SystemVerilog

Verification methodologies : OVM, UVM

EDA Tools : Xilinx ISE 13.1, Questa, Cadence

Virtuoso

VIPs : PCIe Gen3, AMBA AXI-4

Projects (Academic):-

Layout design of a standard cell (OAI321) using Cadence EDA Tools:-

Role : Design Compiler

Tool used : Cadence Virtuoso-180nm

Description: - : Full Custom Design using UMC (0.18?m) Technology was

implemented. The Standard Cell OAI321 Schematic and layouts were designed

in Cadence Virtuoso and simulated for schematic as well as layout using

Cadence Assura and then the Design Rules Checks (DRC) and Layout vs.

Schematic (LVS) were verified.

Publications:-

. K Balraj, Nanhe Lal, Ashish Raman, " Wide Tuning Range CMOS VCO for

Radio Frequency Application", International Journal of Computer

Applications IJCA (0975-8887) Volume 67-No.13, April 2013

Workshop, Training and Seminars:-

> Attended a national level workshop on Xilinx Partial Reconfiguration,

for 3days at VIT UNIVERSITY, Vellore, sponsored by Coreel Technology

in Feb 2012.

> Participated as a volunteer in a workshop on Digital and Analog VLSI

Design Flows organized by SMDPII at NITJ, an initiative of MCIT,

Government of India, from 29th November to 30th December 2011.

Relevant course Work and Teaching Assistance at NTIJ:-

V Digital Systems Design

V Digital Integrated Circuits

V Hardware Descriptive Language(HDL)

V VLSI CAD Lab I & II

V Switching Theory and Logic design Lab

Areas of interest:-

V ASIC and SOC level Verification Engineering

V Physical Design Engineering

V Analog Design Engineering

V RTL Design Engineering

Achievements and Activities:-

> Qualified Graduation Aptitude Test in Engineering (GATE):

. Year 2010 percentile:-96

. Year 2011 percentile:-84.32

> Recipient of MHRD, Government of India scholarship in post graduation.

> Member of discipline committee for various events in school and

college.

Personal profile:-

Name : Balraj Kurva

Father's Name : Hanmanthu kurva

Gender : Male

Nationality : Indian

Date of Birth : 27/06/1988

Languages Known : English, Hindi, Kannada and Telugu

Hobbies : Playing Shuttle Badminton,

Table Tennis, Chess

Watching Tennis, Listening Music, Net surfing

Address for Communication : K Balraj

H-

No: 8-100, Pulimamidi,

Makthal

(T), Utkoor (M),

Mahaboob Nagar- 509353.

Andhra

Pradesh.

Present Location : Bangalore

Current CTC : 3.8 Lakhs

Expected CTC : 6.8 Lakhs

Notice period : 1 month

Declaration

I believe that I have the competitive drive in me. Together

with my analytical ability and technical knowledge I believe that I can

deliver my best for the development of our organization. I assure that

the information provided in this resume is correct to my best knowledge.

(Signature)

Balraj Kurva[pic]

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