SHREEMANT

Email: acdihc@r.postjobfree.com

Mobile: +91-812*******, 962*******

Landline: 012*-*******

Career Objective:

A career opportunity which demands the best of my professional ability in

terms of technical and analytical skills and helps me in enhancing my

current skills.

Technical Skills:

. Languages known Verilog HDL, System Verilog.

. Methodology: Universal Verification Methodology (UVM).

. Digital Electronics, Basic Electronics.

. Tools: Model Sim, Questa Sim

. Operating system: Linux(Ubuntu), Windows 98/2000/XP/7

Academic Qualification:

. Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore

. B.Tech in Electronics & Communication with 67% from IIMT College of

Engineering, Greater Noida affiliated to GBTU.

. Passed XII from KHAITAN PUBLIC SCHOOL Noida (C.B.S.E.) with 80% in

2008

. Passed X from KHAITAN PUBLIC SCHOOL Noida (C.B.S.E.) with 90% in 2006

Major Projects:

1. Title: Router 1X3 Design and Verification:

. Team size: 2 members.

. Design: In this project we designed a Router (1X3) using Verilog HDL

language. Router is a device that forwards data packets between

computer networks. The router comprised of one input data port

(Packet) and three output data ports for the packet to be routed to

its destination.The Packet comprised of 3 parts Header, Payload,

Parity each of 8 bits width and length of the payload can be extended

between 1 byte and 63 bytes.

. Verification: Test bench written in Verilog for verification.

Verification also done with Methodology(UVM) by creating new

verification plan.

. Tools Used: Model Sim.

2. Title: RAM SoC Verification:

. Description : The Design Under Test (DUT) for this verification test

bench is RAM SoC . It includes four instances of 4096 x63 RAM chip.

. Methodology: UVM

. HVL : System Verilog

. Architected the class based verification environment using UVM

methodology.

. Verified the RTL module using the UVM class based TB.

. Generated functional and code coverage for the RTL verification sign-

off

. Tools Used: Model Sim, Questa - Verification Platform and ISE

3. Title: Dual Port RAM Verification:

. HVL : System Verilog

. Architected the class based verification environment using UVM

methodology.

. Verified the RTL module using System Verilog.

. Generated functional and code coverage for the RTL verification sign-

off

. Tools Used: Model Sim, Questa - Verification Platform and ISE

4. Title: UART-16550 (Universal Asynchronous Receiver/Transmitter) IP

Core Verification:

. Description: This core can operate in 8 bit or 32 bit bus data mode.

The 32 bit mode is fully WISHBONE compatible.

. Methodology Used: Universal Verification Methodology(UVM)

. Sequences for configuring the registers of the UART.

. Developed Coverage Model and Scoreboard.

. Features verified: Half Duplex Mode, Full Duplex Mode and Loop Back

Mode, Transmission and Reception with Parity and Stick Parity Error.

Break Error, Frame Error and Overrun Error.

5. Title: GSM Based Home Appliance Control:

. Team size: 4 members.

. Description: This project is designed to make home automation easy to

control when a user is not at home. The project is designed to allow

easy use of a mobile phone to control appliances in the home. One can

switch on and switch off the devices using the GSM mobile.

. Hardware Used: 89S52 microcontroller, GSM phone.

. Software Used: Keil u-vision 3.0, PRO51 programmer.

Summer Training:

. Organization: Telephone Exchange BSNL, Noida.

. Duration: Four weeks (20th June 2011 to 27th July 2011).

. Description: In the summer training done at BSNL I studied about the

various landline connections in Noida and nearby exchanges. I was also

given the idea of the various machines. I covered topics like

Multiplexing, Modulation, Fiber optics communication, Mobile

communication, Telecommunication network. I was also given the

knowledge of handling various faults in communication system.

Extra-Curricular Activities:

. State level Cricket player (played for Meerut District,U.P).

. Scholar badge holder class 10th.

. Participated in science Olympiads.

. Attended SSB interviews for Army and Navy.

Hobbies:

. Listening to music.

. Playing cricket.

. Travelling.

Strengths:

. Problem solving abilities.

. The potential to grow.

. Good communication skills.

Personal Details:

Name : SHREEMANT

Father's Name : Mr. ANIL SHARMA

Date of Birth : 06th September 1990

Sex : Male

Marital Status : Single

Languages Known : English & Hindi

Declaration:

I hereby declare the information mentioned above is true to the best of my

knowledge.

SHREEMANT

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