RESUME

NIRMAL MALLICK

Personal Data:

Father’s Name : Mr. Benudhar Mallick

Mother’s Name : Manjulata Mallick

Date of Birth : 07.05.1991

Sex : Male

Nationality : Indian

Marital Status : Single

Permanent Address:

S\O- Mr. Benudhar Mallick,

AT\PO- Andhara,

Dist.:- KendraPara

Orissa

Pin- 754240

Present Address:

Plot# 27,

Ground Floor,

Opp.To Pragathi Nagar,

Chikkathogur Road,

Bangalore-560100

Contact Numbers:

Mobile :+91-890*******

Email ID:

acdgfu@r.postjobfree.com

CAREER OBJECTIVE

To work in your esteemed organization, I want to be the best performer of the field in which I would work and grow up with the progress of your organization.

EDUCATIONAL PROFILE

Degree : B.Tech in E&C

Discipline : Electronics & communication Engg.

Percentage : 63% aggregate

Institution : KIST, Bhubaneswar

Board : BPUT,ODISHA

Year Of Completion :2012

Course : Plus Two (12th Standard)

Discipline : Science

Per. of Marks : 55.00 % aggregate.

Institution : Times Residential collage, Bhubaneswar

Board : C.H.S.E,ODISHA

Year Of Completion :2008

Course : Matriculation (10th Standard)

Per. of Marks : 52% aggregate.

Institution : B.M. High school

Board : B.S.E,ODISHA

Year Of Completion :2006

Strengths: Good Interpersonal skills, Effective time management, Dedicated & Hard working

SHORT TERM COURSE

VLSI (TWO MONTH) from Central Tool Room &Training Center, Bhubaneswar.

LONG TERM COURSE

Maven Silicon Certified Advanced VLSI Design and Verification course and internship

From Maven Silicon VLSI Design and Training Center, Bangalore.

Year: Nov 2013

EXPERIENCE

Six month experience in Maven Silicon Softech Pvt Ltd.

PROJECT DONE

VLSI PROJECTS:

SPI Controller Core Verification

HVL: System Verilog

EDA Tools: Modelsim, Questa -- Verification Platform

Description: The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data transfer at both edges of clock. This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register. The SPI Core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

GPIO Controller Core Verification

HVL: System Verilog

EDA Tools: Modelsim, Questa -- Verification Platform

Description: The GPIO Controller Core is an interface between ABP compatible Master Device and ABP interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit. It supports data latching and data transfer at both system clock and external clock. This core can be configured to connect with 32 slaves. The GPIO Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register. The GPIO Core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: System Verilog

EDA Tools: Modelsim, Questa -- Verification Platform and ISE

Description: The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel0, channel1 and channel2.

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using System Verilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

ACADEMY PROJECT:

Home Security And Maintenance Using GSM

Description: Aim of the design is to develop a system based on Embedded micro controller (8051), which is used for controlling various loads of home using GSM service also it can send a SMS whenever any intrusion is detected.

Responsibility: Hardware integration and testing

TECHNICAL SKILLS

Knowledge in Cmos Layout and simulation.

Knowledge in Industrial Instrumentation.

A depth in Microprocessors and Micro controllers, Assembly level programming.

Knowledge in software design tools like keil, Matlab 6.5, Xilinx. Micro wings.

Basic knowledge in Design For Testability (DFT) .

VLSI DOMAIN SKILLS

HDLs: Verilog and VHDL

HVL: System Verilog and PSL

Verification Methodologies: Coverage Driven Verification Assertion Based Verification

TB Methodology: UVM

EDA Tool: ModelSim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design methodologies.

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis, ABV

ACHIEVEMENTS

Mr. Fresher award in first year welcome ceremony.

first prize in inter college debate competition

Received the best performer award from Maven Silicon during the VLSI Design course

LANGUAGES KNOWN

English, Hindi, Oriya

INTERESTS

Reading, Listening music, Enjoying nature

DECLARATION

I hereby declare that all the data and information provided above are true and correct to the best of my knowledge and I hold responsible myself for any irregularities if found.

Date:

Place: Bangalore NIRMAL MALLICK

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