A.Yaswanth Reddy

H.No.**/***/**,simhapuri colony, kadapa-516002

Tel: +918*********, +917*********, E-mail: acdge9@r.postjobfree.com

OBJECTIVE

To give justice to my talent by reaching the top levels in

engineering and create a distinguished identity.

ACADAMIC PROFILE

Degree : M. Tech (Micro Electronics & Control

Systems).

College : PES Institute of Technology, Bangalore.

University : VTU Belgaum.

Percentage : 72.8% (Up to 3rd SEM).

Degree : B. Tech (ECE).

College : Vaagdevi Institute of Technology & Science,

Proddatur.

Year of Passing : 2012.

University : JNTU Anantapur.

Percentage : 72.3%.

Pre University : Science (MPC).

College : Sir C.V.Raman Junior College, Tadipatri, AP.

Year of Passing : 2008.

University : Board of Intermediate, Hyderabad, A.P.

Percentage : 92.7%.

X Class

School : Sri Sai Vijetha High School, Tadipatri, A.P.

Year of Passing : 2006.

University/Board : Secondary School of Education, Hyderabad, A.P.

Percentage : 87.6%.

SKILLS SET

Scripting Language : Perl.

Language : C, VHDL, Verilog, System Verilog.

Methodology : UVM.

Area of Interest : Digital Design, RTL Coding, STA, Digital

Communication.

Tools : Xilinx, Model Sim, Lab View.

ACHIEVEMENTS

. Secured 114th Rank in APRJC Exam.

. Received "Sir Isaac Newton" prize in the academic year 2010-2011 for

securing best GATE rank in my college.

CO-CURRICULAR ACTIVITIES

. Participated in various NSS & college activities actively.

. Participated in ROBOT designing workshop in JNTUP University (KADAPA).

. Participated in Industrial visit in HMT Company-Hyderabad, for the

project.

. Had given seminars on wireless communication topics like "Gi-Fi".

PROJECTS

. HDB3 decoder implementation using VHDL.

. Digital Code Lock implementation using VHDL.

. MODULAR XOR LFSR implementation using Verilog.

. Ethernet MAC 10/100 Mbps implementation using Verilog.

. UART implementation using Verilog.

. RS232 implementation using Verilog.

. VGA Controller implementation using Verilog.

. Router design and verification using Verilog and UVM.

STRENGTHS

0. Good Leadership Qualities, hardworking & teamwork.

1. Working for results with a good plan & timely execution.

2. Optimism & positive attitude.

PERSONAL PROFILE

Fathers Name : A. Rami Reddy.

Date of Birth : 11 Jun 1991.

Languages Known : Telugu, English, and Hindi.

DECLARATION

I do hereby declare that the above-mentioned

information is true to the best of my knowledge and I bear the

responsibility for the correctness of the above-mentioned information.

Place : Bangalore

Date :

A.YASWANTH REDDY

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