SIVA KANTAMREDDY

#*, *** ************ *.*,

#***/** *.*.* Complex,

Samrat Layout, Arekere Gate, Mobile no: 855-***-****

Bangalore -560076. acdg45@r.postjobfree.com

Career Objective:

Looking for a responsible position as a Front End engineer with a view to utilize and

enhance my skills to meet company goals and objective with full integrity and zest

Summary of Qualifications:

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and Reusable Test benches in

System Verilog

Good knowledge in verification methodologies (UVM)

Experience in using industry standard EDA tools for the front-end design and

verification

VLSI Domain Skills:

HDLs : Verilog

HVL : System Verilog

Verification : Coverage Driven and Assertion Based Verification

TB Methodology : UVM

EDA Tools : Xilinx-ISE, Model-Sim and Questa Sim 10.0b

Domain : ASIC/FPGA Design Flow

Knowledge : Digital Circuit Design and Verification methodologies

RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis, Perl and C-shell basics

Platform : Linux and Ubuntu

Professional Qualifications and Experience:

Member of institute of electrical and electronics engineers (IEEE) during 2008-2009

6 months Industry Standard Advanced VLSI Front-end Design and Verification

Training at RV_ VLSI Design Centre, Bangalore

Educational Qualifications:

Year Of % of

Qualification Name of university School/College

Passing Marks

Jawaharlal Nehru

Dadi institute of

Degree Technological engineering and 2008-12 68.78%

technology.

University- Kakinada

Board of Intermediate Sri chaitanya junior

Intermediate 2006-08 90.8%

Education college. gajuwaka.

Vasavi Bala Vihar

Board of Secondary

High School,

Tenth 2006 75%

Education

Anakapalli.

VLSI Projects:

verification of SUB-SYSTEM

HDL : Verilog

HVL : System verilog

: Modelsim, Questa – Verification Platform

EDA Tools

Methodology : UVM

Description: The sub-system is an integrated implementation of three standard

communication interfaces namely UART, I2C, SPI on the WISHBONE system bus

accessed through a AHB-WISHBONE bridge. The master on AHB side can

communicate through internal programmable registers of each interface,write and

read operations are performed for each protocol.

Deliverable/Challenges Faced:

Implemented sequence library, tests and written test cases for different

protocols

Understanding the specification

Checking status of registers in slaves while driving data and receiving data

Randomization of signals and their analysis and effective debugging using

.log files

Verification of FIFO using verilog, system verilog, UVM methodology

HDL : Verilog

HVL : System verilog

: Modelsim, Questa – Verification Platform

EDA Tools

Role : Understanding the FIFO operation and building environment

Deliverable/Challenges Faced:

Synchronization of tasks while verifying with verilog and stimulus generation

Connecting the components and driving the data from generator to driver

Building up environment and connecting components, making agents active or

passive

Vedic Multiplier Design and Verification

HDL : Verilog

HVL : Verilog

: Modelsim, Questa – Verification Platform

EDA Tools

Implemented the Vedic multiplier using Verilog HDL independently

Synthesized the design

Accomplishments:

Qualified in GATE-2013

Won a third price in TECHNOGRILL competition conducted by Andhra University

Extra Curricular Activities:

Given a paper presentation on OFDM at GRM-IT campus

Participated in IEEE-XTREME a 24 hours coding program organized by DIET-IEEE

forum in our college in 2nd year

Participated ROBOTIC-EVENT in 2nd year conducted by IIT KHARAGPUR

Participated EXPOSURE-EVENT in 3RD year organized by GAYATRI VIDYA

PARISHED COLLEGE

Strengths:

Positive Attitude and self confidence

Disciplined & Good Etiquette

Hobbies and Interests:

Reading books and Travelling

Personal Details:

Sex : Male

: 07th November, 1990

Date of Birth

Marital Status : Single

Languages Known : English, Telugu

Address : D:no 9-5-37,kotni veedhi,

Station road, Anakapalli,

Visakhapatnam-531001

Date:

Place: (K.SIVA)

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