S. ADHITHYA

E-mail: accwjv@r.postjobfree.com

Mobile: 979*******

085********

Summary of Qualifications:

> A skilled, talented and knowledgeable Engineering candidate looking to

furnish my knowledge and skills for the betterment of your esteemed

organization

> Good understanding of the ASIC and FPGA design flow

> Experience in writing RTL models in Verilog HDL and Testbenches in

SystemVerilog

> Very good knowledge in verification methodologies

> Experience in using industry standard EDA tools for the front-end

design and verification

VLSI Domain Skills:

HDLs: Verilog and VHDL

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification

TB Methodology: UVM

EDA Tool: Modelsim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design

methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional

Coverage, Synthesis,

Static Timing Analysis, ABV

EDUCATIONAL QUALIFICATIONS:

Exam/Degree University/

Board Name of the Institution Period of study Percentage/CGPA of marks

obtained VLSI Frontend Desinging and Verification Trainee Individual

Course Maven Silicon, VLSI Design and Training Center July 2013- December

2013

60.5%

B.E

(ECE) Anna University

Sri Ramakrishna Institute of

Technology 2009-2013

66.9% HSC State Board

Jaycee Hr. sec. School 2008-2009

81.30% SSLC State Board Seventh Day Adventist Hr. Sec. School 2006-

2007

82.80%

SKILLS:

TECHNICAL QUALIFICATIONS:

Programming Languages : C, C++,VERILOG,UVM.

Software's known : MODELSIM, XILINX, PSPICE and MAT

LAB.

Web Technology : HTML.

AREAS OF INTEREST:

. VLSI

. Microprocessors& Microcontroller

Course completed:

July 2013- December 2013, Maven Silicon, VLSI Design and Training Center

VLSI Projects:

Dual Port RAM - verification

HVL: System Verilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

> Implemented the Dual Port Ram using Verilog HDL independently

> Architected the class based verification environment using system

Verilog

> Verified the RTL module using System Verilog

> Generated functional and code coverage for the RTL verification sign-

off

Router 1x3 - RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa -- Verification Platform and ISE

Description : The router accepts data packets on a single 8-bit port called

data and routes the packets to one of the three output channels, channel0,

channel1 and channel2.

> Architected the design and described the functionality using Verilog

HDL.

> Architected the class based verification environment using system

Verilog

> Verified the RTL model using SystemVerilog.

> Generated functional and code coverage for the RTL verification sign-

off

> Synthesized the design

UART- IP Core - Verification

HVL: System Verilog

EDA Tools: Modelsim.

The UART IP core consists of a transmitter, a receiver, a modem interface,

a baud generator, an interrupt controller, and various controls and status

registers. This core can operate in 8-bit data bus mode or in 32-bit bus

mode, which is now the default mode. It is an interface between wishbone

compatible UART transceiver, which allows communication with modem or other

external devices, like another computer using a serial cable and RS232

protocol. The UART core RTL is technology independent and fully

synthesizable.

> Architected the class based verification environment using system

Verilog

> Verified the RTL module using System Verilog

> Generated functional and code coverage for the RTL verification sign-

off

Engineering Projects:

Project Title : Medical Image Retrieval Using Fuzzy Object

Relational Database Management System

Team size : 4 Members

Duration : 7 months

Project description : Using FORDBMS we process the input image with

respect to query image and produces the resultant output. Image retrieval

process consists of a query example image, given by the user as an input,

from which low-level image features are extracted. We used X-ray images

using fuzzy approach to produce accuracy in output.

ACHIEVEMENTS

Academic

. Attended a seminar on "WIRELESS NETWORKS ON RURAL APPLICATIONS" in

Coimbatore.

. Attended a National Conference " VLSI AND IMAGE PROCESSING " in

Chennai.

. Attended an International Conference "NANO ELECTRONICS" at Coimbatore.

. Participated in the paper presentation titled "MEDICAL IMAGE RETRIEVAL

USING FUZZY OBJECT RELATIONAL DATABASE MANAGEMENT SYSTEM" on National

Level Technical Symposiumat Coimbatore.

. Participated in one day exhibition cum science programmes on "SCIENCE

UNLIMITED- VISTAS IN BIOLOGICAL SCIENCES".

. Completed my C and C++ course in NIIT Coimbatore during the academic

year 2012.

Sports

. Got second prize in High Jump.

. Got third prize in Long Jump.

. Attended a marathon for CRPF Jawans.

Cultural

. Participated in WIZ QUIZ competition.

. Got first prize in "FLOWER POT ARRANGEMENT"

STRENGTHS

. I can adapt any environment given to me.

. I'm a quick learner.

PERSONAL PROFILE:-

Father's name : S.SURULI RAJAN

Gender : Male

DOB : 24-1-1992

Nationality : Indian

Languages Known : English, Tamil.

Permanent Address : B-43, Anna nagar Housing unit, Edayarpalayam,

Coimbatore-25.

DECLARATION:-

All the details furnished above are true to the best of my knowledge.

Place:

Yours sincerely

Date: S.ADHITHYA

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