RESUME

RAGHU VENKAT SAI KIRAN EPI

Email: accvhp@r.postjobfree.com

Mobile No: +91-903*******

Career Objective:

Looking forward for an opportunity in a challenging environment, where i can utilize my

skills in contribution effectively to the success of the organization and also for the improvement

of my personal skills.

Qualifications:

Course / University / School / College Year of Aggregate

Specialization Board Passing

M.TECH JNTU Sri Sai Jyothi Nov 79%

HYDERABAD Engineering college, 2012

[VLSI]

Hyderabad.

71%

B.TECH JNTU Sri Vasavi June

Engineering college, 2009

[E.C.E] KAKINADA

Tadepalligudem.

85%

INTERMEDIATE Board of Aditya junior College, May

Intermediate Mandapeta. 2005

[M.P.C]

Education

SSC Board of April 81%

Sri Siddhartha High

Secondary 2003

School, Alamuru.

Education

Technical skills:

1) HDL Known : Verilog.

2) Functional Verification Tool : Active HDL, Xilinx 10.1 ISE.

3) FPGA Prototyping : Xilinx ISE 10.1

3) Operating Systems : Unix/Linux, Windows-XP.

4) Programming Languages : C,Sql.

5) Scripting Languages : Unix.

6) Database : Oracle.

Achievements & Accomplishments:

1) Published Technical Paper in International Journal of Engineering Research and

Technology (IJERT) in Sep 2012.

2) Obtained 1st prize in Pragathi Talent Test in Schooling.

3) Acquired an GATE Score -400 (92%) in 2010.

4) Winners in Soft ball in zonal grig held by East Godavari athletic association.

5) Runners in Hand ball in zonal grig held by East Godavari athletic association.

6) Actively participated in “Two-day’s Work Shop on Digital Image Processing &

Application On 7th,8th Feb 2011 ” conducted by Sri Sai Jyothi Engineering College,

Hyderabad.

7) Obtained certificate “grade-good” in Schooling at ‘MATHEMATICS TALENT

TEST’ conducted by “RAMANUJAN MATHEMATICS ACADEMY”.

Project Thesis:

1. M.TECH PROJECT

Project Title Modelling and Simulation Experiment on a Built-In Self

Test for Memory Fault Detection in SRAM.

Client 3EMR,Hyderabad.

March Algorithms are implemented for testing memory Faults

Description

models like Static and Dynamic .To test these type of algorithms

a newly micro-coded BIST Architecture is Presented .In this

project My aim to find all dynamic faults which are not covered

by March SS algorithm by changing its instruction length and

these complete operation is performed in Two modes 1)Normal

Mode. 2) Test Mode.

B.TECH PROJECT

2.

Designing of I2C Master Core using FPGA.

Project Title

Clarion Park,Hyderabad.

Client

I2C is a two-wire, bi-directional serial bus that provides a

Description

simple and efficient method of data exchange between

devices. It is most suitable for applications requiring

occasional communication over a short distance between

many devices. The I2C standard is a true multi-master bus

including collision detection and arbitration that prevents

data corruption if two or more masters attempt to control

the bus simultaneously.

Role Project Leader

Personal Details:

Name Venkat Epi

Date of Birth 19/03/1988

Nationality Indian

Single

Marital Status

E.Prasad

Father’s Name

Hyderabad

Address

English,Telugu

Languages Known

Male

Gender

Playing Cricket,Badminton.

Hobbies

I here by declare that above furnished information is true up to the best of my

knowledge.

Place:

Date:

[Venkat Epi]

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