Venkata KondaReddy Palle

+91-890*******

#**, *** *****, ******* ****,

accv1m@r.postjobfree.com

Bannerghatta Road, Bangalore-560076

CAREER OBJECTIVE

To develop my career as a VLSI Engineer where I will be a valuable team member,

contributing quality ideas and work for the organization growth as well as individual.

EDUCATIONAL QUALIFICATIONS

Institute

Year/Period Course Percentage/CGPA

2011-2013 M.Tech in VLSI Design and National Institute of Technology, 8.8

Embedded Systems Jamshedpur

2005-2009 B.Tech (ECE) Madanapalli institute of technology & 69.36 %

science, JNTUA, AP

2003-2005 Intermediate St. Joseph’s Junior college, 93.3 %

Mariapuram,Kadapa AP

2002-2003 S.S.C Sri Sankaras High school, duvvur, AP 86.83%

SKILL SET

HDLs: Verilog

HVL: System Verilog

TB Methodology: UVM

Verification Methodologies: Coverage Driven Verification,

Assertion Based Verification

EDA Tool: ModelsimSE, QuestaSim, Xilinx ISE, Cadence, Tanner

Domain: ASIC/FPGA Design Flow, Front End Design, RTL Coding,

Functional coverage & code Coverage, Synthesis, and Static

Timing Analysis

Scripting: Perl, Bash Shell

VLSI PROJECTS

1. AHB2APB Bridge Verification:

METHODOLGY: UVM

EDA Tools: QuestaSim – Verification Platform

Description:

The AHB2APB interfaces the AHB to the APB buffering address, control and data from

the AHB, driving the APB peripherals and returning data and response signals to the

AHB. It also decodes a peripheral's address map to select the peripheral. If any further

decoding is required on the selected peripheral, then this is done by the peripheral itself.

Architected the class based verification environment using UVM

Verified the RTL module using UVM

Venkata KondaReddy Palle

+91-890*******

#15, 2nd cross, Arekere Gate,

accv1m@r.postjobfree.com

Bannerghatta Road, Bangalore-560076

Generated functional and code coverage for the RTL verification.

2. Router 1X3- RTL Design and Verification:

HDL: Verilog

HVL: System Verilog

METHODOLGY: UVM

EDA Tools: QuestaSim – Verification Platform and Xilinx ISE- Design

Implemented the router have three client using Verilog,Synthesized the design

Verified the RTL model using System Verilog and UVM methodology.

Generated functional and code coverage for the RTL verification.

3. Dual Port RAM - RTL Design and Verification

HDL: Verilog

HVL: System Verilog

METHODOLGY: UVM

EDA Tools: QuestaSim – Verification Platform and Xilinx ISE- Design

Implemented the Dual Port Ram using Verilog HDL.

Verified the RTL module using System Verilog and UVM methodology.

Generated functional and code coverage for the RTL verification sign-off

ACADEMIC PROJECTS

FPGA based Gate and RTL Level Fault Injection Technique and Tool for Fault

Tolerance Designs (M.Tech)

The Aim of the project is to design a FPGA – based fault injection technique and tool

which allows the designers to inject the faults at gate and RTL level, where structural model

of a digital system is written in VHDL. By using this tool we can observe the system

behavior before and after injecting the faults into the fault tolerance designs.

As a case study double ALU based fault tolerance processor was taken and evaluated

using Spartan FPGA.

• Simulation software - Modelsim Xilinx Edition (MXE)

• Synthesis, P&R - Xilinx ISE

• On chip verification - Xilinx Chipscope

• Hardware - Xilinx Spartan 3 Family FPGA board

Line follower robot (B.Tech)

Line follower robot is a machine that can follow a path. The path can be visible like a

black line. Sensing the path and direction the robot to stay on course, while constantly

correcting wrong moves using feedback mechanism forms a simple yet effective closed loop

system. Flash based microcontroller AT89C51 is the heart of monitoring circuit. Coding is

done by using KEIL MICROVISION V.3 software and Hardware circuitry is implemented

using AT89C51 microcontroller. Practical applications of a line follower: Automated cars

running on roads with embedded magnets; guidance system for industrial robots moving on

shop floor etc.

Trainings

Venkata KondaReddy Palle

+91-890*******

#15, 2nd cross, Arekere Gate,

accv1m@r.postjobfree.com

Bannerghatta Road, Bangalore-560076

• Pursued Training Course on VLSI DESIGN AND VERIFICATION at Maven

Silicon.

• Attended the short term course on VLSI CAD Tools held in NIT Rourkela.

Publications and Conferences

• FPGA based Gate and RTL Level Fault Injection Technique and Tool for Fault

Tolerance Designs published in International Journal of Computational Intelligence

and Information Security, March 2013, Vol. 4 No. 3, and ISSN: 1837-7823

• Participated in a National Conference on Advances in Engineering and

Technology (NCAET -2013) held at MITS institute of Polytechnique, Rayagada.

Personal Details

Father Name : Sri P.Venkata rami reddy.

Mother Name : Smt. P.Guramma

Permanent Address : Bheemunipadu (village),

s.t.palli (post),

Duvvur (m),

Kadapa (district),

Andhra Pradesh

Contact : +91-888*******

21th April 1988

Date of Birth :

Sex : Male

Marital Status : Single

Nationality : Indian

Languages Known : Telugu, Hindi and English

Declaration

I hereby declare that the above information and particulars are true and correct to the best

of my personal knowledge and belief.

Date:

Place: P Venkata

KondaReddy

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