MANOJ B

Contact **-*-***/***/**, Shankerbagh Voice: (91-965-***-****

Information Arundathi colony, Huppuguda. E-mail: accssa@r.postjobfree.com

Hyderabad 500053, India

Research 1. Advanced Micro controllers and their Bus protocols.

Interests

2. Wireless Communications Design and Development.

3. Model Order Reduction Techniques for VLSI Technology.

4. Low Power circuit design on Integrated Circuits.

5. Multi-core Processors.

Education 1. Bachelor of Technology (B.Tech) IV year, Vardhaman Col-

lege of Engineering (VMEG),shamshabad affiliated to Jawarhar-

lal Nehru Technology University (JNTUH), Hyderabad, India

Department of Electronics and communications, May 2014 (expected)

.. 74%(up to 7 semesters)

2. +2,Board of Intermediate Examination (BIE),2010 Hyderabad,

India.

.. 90 %

th

3. 10,Central Board of Secondary Education(CBSE),2008 Hyder-

abad, India.

.. 80 %

Computer 1. EDA Tools:

Skills Cadence frontend and backend tool set

For Physical design: - SOC Encounter

Encounter Timing system,

NanoRoute Router,

Physical Verification system,

VoltageStorm Power Verification

For Netlist generation and verification: -

Encounter RTL Complier

PSpice A/D and Advanced Analysis.

For Analog design : - Virtuoso Analog Design Environment(ADE)

Virtuoso Schematic editor,

Virtuoso Layout Suite,

Assura Physical Veri

cation system,

Virtuoso Analog Design Environment(ADE),

Virtuoso Visualization and Analysis(ViVA),

Virtuoso Spectre Circuit Simulator,

Virtuoso AMS simulation (Analog Mixed-Signal)

Virtuoso UltraSim Full-Chip Simulator

Virtuoso Multimode Simulation,

Incisive Verification Kit ( Verilog XL, SimVision )

2. Hardware Description Language: Verilog, VHDL, Verilog AMS.

3. Operating Systems: Windows, Linux, Unix .

4. Programming Languages: C, JAVA, MATLAB, Simulink.

5. Scripting Languages: Shell scripting(csh), Tcl.

6. Application Development: Code Composer Studio simulation & mod-

eling.

Books Written 1. With guidance of Professor Dr J V R Ravindra, had written “Manual

on RTL compiler” during july-sept 2013.

Book Description: This book gives a quick reference for synthesizing a

HDL code . An example of 128 bit counter is also taken as reference and

synthesized with least congestion, area and power.

Honors and 1. Qualified Cadence VLSI Certification Program (CVCP)-2013, certified

Awards by Cadence Design Systems, Bangalore

2. Member of Indian Society for Technical Education (ISTE).

3. Organized Robotics club and Antenna house during the technical fest.

4. Second prize in Paper Presentation on CALORIEMETER during tech-

nical fest in BITS, Pilani.

5. First prize in ROBO- Tera firma in National level competition conducted

during Technical fest in our college.

Projects 1. Project Partners : Manoj, Srikanth, Shashank, Zubair

Project title :APB - UART Interface Protocol in mobile phones.

Project Description: This is a serial to parallel / parallel to serial com-

munication protocal between Advance High-performance Bus(AHB)

to Advance Peripheral Bus (APB2 or APB) bridge to Universal Asyn-

chronous Receiver and transmitter (UART) protocal using Advanced

Micro controller Bus Architecture (AMBA) 2.0

AHB gets connected to APB by AHB to APB bridge. Processor gets

connected to serial communication device i.e. UART (modem) by this

bridge. The project gives a clear idea about how the this bridge is

connected with three major components of the UART block namely

Baud generator, Receiver and Transmitter.

The most important part of this protocol is that the speed of receiver

has to be 16 times greater than the speed of operation of transmitter

My role was to design the architecture for the APB Logic block, Trans-

mitter, write the RTL code for Transmitter and draw the state ma-

chine of Receiver block .

2. Project Partner : Shashank, Manoj

Project title : Interpretation of Redundant Number System

(RNS) in Advance Security Systems.

Project Description : Redundant number system deals with numer-

ical methods to interchange the RADIX and DIGIT SET of a given

number, thus the Redundancy (randomness) of a number or a char-

acter can be done . The carry save operations are also done in this

algorithm when the radix is changed to higher order .For a radix - n

number system, the digit set is [0,n-1] .

In this project the digit set and as well as radix is changed to a num-

ber of radix -r and digit set [a,b] where a,b can be any number and

is transmitted, until we give the value of n, a, b the data cannot

be decoded .This is popularly been used in ADVANCE SECURITY

SYSTEMS.

My role was to synthesize the code with least congestion and power

and do the numerical part and cross check the redundant data with

the retrieved data during simulation.

3. Project Partners : Manoj, Sankhyayani .

Project title : Implementation of Model Order Reduction(MOR)

for VLSI Techniques : h - gamma, PRIMA

Project Description: The project deals with optimization of complex

networks, with least number of poles involving timing, power and area

constraints. The various techniques followed for model order reduc-

tion are ” h - gamma,PRIMA, PRIMO”. Project(h -gamma) deals

with probability distribution functions that gives out the net delays.

Passive Reduced-Order Interconnect Macro modeling Algorithm (PRIMA)

describes an algorithm for generating provably passive reduced-order

N-port models for RLC interconnect circuits. It is demonstrated that,

in addition to macro model stability, macro model passivity is needed

to guarantee the overall circuit stability once the active and passive.

SPICE(Simulation Program with Integrated Circuit Emphasis) imple-

mentation of simple circuits to find out the net delays, timing path

was calculated in this project. Moments about the origin and central

moments were found to relate the time delays with the nodes, the nth

order coefficient of the quadratic equation found by probability func-

tion is equal to time constant of the nth node .

My role was to calculate the net delays, time constant at every node

and give a detailed analysis of TIMING PATH, which was used in

cross checking with SPICE.

Personal 1. Name : B Manoj

Information

2. Mother’s name : B Nageswari

3. Father’s name : B Chandra sekhar

4. DOB : 28 May 1993

5. Languages known : Telugu, English, Hindi

6. Hobbies : Reading and Sports

Manoj B

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