Kamlesh Pathak

STC-****, Sun Tower,

Shipra Sun City, Indirapuram Cell: +91-981*******

Ghaziabad, Utter Pradesh 201014 Email accr2o@r.postjobfree.com

CareerAccomplishments

• Interdisciplinary Electronics and Software Engineer with over 11 years of experience in

semiconductor industry around System level design tools, flows and methodologies.

• Expertise in being at ease in high stress, fast-paced environments with emerging and multiple

responsibilities in multicultural environment.

• Expertise in IP-XACT(IEEE1685), C++, SystemC, TLM, modelling, functional verification and

SoC/Virtual SoC integration.

• Expertise in various industry on-chip bus standards from ARM(AHB,APB,AXI,ACE)

• Expertise in developing, maintaining and deploying tools and methodologies around IP-XACT to

automate IP packaging, model generation, test bench generation, SoC/VSoC integration, verification

flows and documentation to reduce the design cycle time.

• Expertise in developing, maintaining and deploying tools and methodologies for complete SoC

architecture exploration flow (traffic, power, cache etc.) for various bus protocols at several

abstraction levels.

• Expertise in interacting with customers, EDA vendors for new requirements and providing

solutions around system level design tools, flows and methodologies.

• Contributing towards IP-XACT(IEEE1685) standard enhancements with other

EDA/Semiconductor industry partners at Accellera System Initiatives. Currently Vice chairing the

Schema Working Group responsible for IP-XACT standard enhancement/authoring for next version.

• Alignment and close cooperation with various EDA partners providing IP-XACT tools (Magillem,

Synopsys, Atrenta, Duolog etc.)

• Good management skills to manage multicultural environment (currently managing a team based

in three different sites, also responsible for people management, appraisals, hiring, mentoring new

joiners etc.)

Scholastic Credentials

• Master of Technology (M.Tech.)in Computer Technology from Indian Institute of

Technology (IIT), Delhi in 2002

• Bachelor of Technology(B. Tech.) in Electronics & Communication Engineering from

G.B. Pant University of Agriculture and Technology, Pantnagar in 2000

Competency Matrix

IP-XACT, XML, XSLT, DITA C,C++,SystemC,VHDL,System Verilog,Java

Perl, TCL/TK, Shell scripting SystemC, TLM, BCA, RTL modeling

Eclipse, GDB SoC/VSoC integration and verification

Linux, Windows Magillem, Simvision, CoreAssembler

Experience Summary

Senior Project Manager, ST Microelectronics Pvt Ltd Nov2012 - till date

Project Manager, ST Microelectronics Pvt Ltd Oct 2010 - Oct 2012

Senior Design Engineer, ST Microelectronics Pvt Ltd Dec 2007 - Sept 2010

Design Engineer, ST Microelectronics Pvt Ltd July 2005 - Nov 2007

Associate Design Engineer, ST Microelectronics Pvt Ltd Jan 2003 - June 2005

Professional Experience

• IP-XACTpackaging tools and methodologies

Aim:To develop tools and methodologies to create IP-XACT descriptions ofcomplex,

parameterized, highly configurable IPs, subsystems and SoCs/VSoC to enable use of IP-XACT based

design flows to create high quality bug free designs with less time to market. Incorporates IP reuse

and 3rd party IPs interoperability in complex SoC design flows. Helps designers to reduce the design

cycle time by identifying the bottle necks of front end design flow and strengthening the scope of

reusability. Address standard limitations by introducing vendor extensions and propose them in

Accellera for next version of standard.

Technology Used : IP-XACT(IEEE 1685), XML, XSLT, Perl, JAVA, Eclipse, Linux, Windows

Key Accomplishments :

Developed tools and methodologies to create IP-XACT description of complex, highly

configurable, parameterized IP, Subsystem and SoC from their functional specifications(Frame maker,

Word, excel, csv and proprietary formats)

Automatically extract register descriptions, interfaces, I/Os, instances, connections etc.

from functional specifications to create IP-XACT descriptions.

Developed tools for schematic/semantic checking, smart diff, merge and patching of IP-

XACT descriptions.

The underlying flow is fully based on IP-XACT description which results implicit

coherency between design teams, also as the flow is automated so it is quickly adaptable for any

specification changes.

Developed tools to automatically generates full SoC memory map document for

designers and customer datasheets in different formats (frame maker, word, pdf, csv or excel format)

from frozen IP-XACT descriptions.

• IP modeling tools

Aim: To develop tools and methodologies to automate the creation of TLM and RTL skeleton of

IPs and subsystems, also automatically generates the minimal verification tool to validate the

generated skeletons.

Technology Used : IP-XACT(IEEE 1685), XML, XSLT, Perl, JAVA, Eclipse, Linux, Windows

Key Accomplishments :

Developed tools to automatically create skeleton of IP and subsystems with full

implementation of IP register bank, decoder and interfaces. The IP designers only need to add the

corresponding functionality to complete the model.

Developed tools to create minimal verification platform for quick validation of generated

skeleton including register bank, decoder and interfaces. Automatically generated full register test

functions are also incorporated.

Easily and quickly adaptable for any design, specification changes.

• IP/SoC Verification tools and methodologies

Aim :To develop tools and methodologies to automate the verification platforms and test benches

generation for complex, highly configurable IPs, subsystems and SoCs/VSoCs in both TLM and RTL

domains, also develop tools to automatically generates the header files and register test cases

in C and System Verilog(UVM) from IP-XACT register description .

Technology Used : IP-XACT(IEEE 1685), XML, XSLT, Perl, JAVA, Eclipse, System Verilog,

UVM, Linux, Windows

Key Accomplishments :

Developed tools and automated flows for creating verification platforms for IPs,

subsystems and SoCs.

Developed tools to generate automatically the configurable C header files for firmware,

software and verification needs, also ensures their portability from SystemC to Silicon.

Developed tools to generate automatically the full C based registers test cases for IPs,

subsystem, SoCs to verify full register bank and interconnections.

Developed tools to generate automatically the UVM register classes with random

sequences for IPs, subsystems and SoCs to quickly generate system Verilog based register test

benches.

Developed tools to automatically create System Verilog based verification env to validate

various RTL register banks and its interfaces.

Developed debug tools e.g. waveform mnemonics generator to ease debugging the

waveforms.

Developed generic traffic injectors, grabbers for AXI based interconnect at various

abstraction levels

Easily and quickly adaptable for any design, specification changes.

• SoC/VSoC integration tools and methodologies

Aim :To develop tools and methodologies to automate the IP configuration, parameterization and

integration to create the complete SoCs/VsoCs and their variants.

Technology Used : IP-XACT(IEEE 1685), XML, XSLT, Perl, JAVA, Eclipse, Linux, Windows

Key Accomplishments :

Developed tools and methodologies to automate the full SoC/VSoC integration flow from

high level tabular description of design (instances and their connections).

Seamless and smooth integration of highly configurable/parameterized IPs/Subsystems

and 3rd party IPs/Subsystems.

Developed robust macros to enable the consistencies check during design capture

phase.

Easily managed various design hierarchies to help place and route phase later in the

flow.

Ensure the generation of both SoC and VSoC from same high level design description to

ensure coherency and use of same high level design capture to create new variants of a given

SoC/VSoC

Easily and quickly adaptable for any design, specification changes.

• SoC Architecture/performance Evaluation Flow

Aim:To developed models and methodologies for early SoC architectural exploration (e.g.

bandwidth, throughput, latencies, interconnect FIFO sizing etc.) for SoC architecture optimization to

enable SoC architects to make final decisions in earliest possible design phase. Supports

architecture exploration for interconnect with various standard on chip bus

protocols(AHB,APB, AXI) and proprietary busses at various abstractions levels(e.g.

TLM/BCA/RTL)

Technology Used: C++, SystemC, TLM, VHDL, Shell scripting, Linux, GDB, Make, Purify,

Valgrind, NcSim, OSCI, ModelSim, VCS, Carbon SoC designer

Key Accomplishments :

Developed generic traffic generator/receiver models to use as master/slaves on

interconnect which takes traffic/memory characterization file as input and generates/receives

that traffic on/from interconnect.

Developed models for communication phase identification and signals toggling to

estimate SOC rough power estimation at early design phase.

Developed models to figure out cache hit/miss to optimize cache memory.

Developed complex, generic and highly configurable SystemC interconnect

models, i.e. arbiters, slaves, data bus size converters etc. to enable early analysis.

Develop tools to probe simulation databases and provide performance figures for

SoC performance evaluation. Also able to generate equivalent transactional debug database

from its signal level database to speed up debugging.

Developed generic Interconnect Latency Simulator to study interconnects

parameters at very early stage of SoC design.

Publications & Awards

• Recurrent neural networks with nonlinear synapses for solving optimization problems,

IETE J RES 49 (2-3): 197-209 MAR-JUN 2003(Won Gold Medal for IETE Best Paper Award,2003).

• Verification and automation improvement using IP-XACT, DVCon 2012.

• IP XACT Tutorial "A Practical Guide to Packaging IP and Assembling SoCs Using the IP-

XACT- IEEE1685 Standard", DAC 2013.

• Paper on “SoC and IP Integration Methods and Tools” accepted for DVCon 2014.

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