Chandan Rajappa

+1-469-***-**** **** Waterview Pkwy, Apt 25111, Richardson, TX 75080 accng0@r.postjobfree.com

Objective

Seeking a Co-op/internship in the field of IC/Processor Design and Verification for spring and summer 2014

Overview

- Over 2 years of focused experience in Circuit Design/Simulations

- Proficient in usage of CAD software

- Experience with programming in Spice, Verilog and Perl

- Well versed with all aspects of VLSI design flow from RTL Synthesis to Manual placement and routing, timing

analysis, library Characterization

Education

Electrical Engineering, University of Texas at Dallas MAY 2014 (expected)

3.8

M.S

Electrical & Electronics Engineering, Visveshwaraya Technological University JUNE 2010

3.9

B.E

Work Experience

July 2010 – July 2012: Systems Engineer at Finacle Division, Infosys Limited

Worked on Finacle, a Banking Software Tool using JAVA and FEB A

Worked in core design team of Finacle E-banking Architecture

Received the GEM award for outstanding performance.

Relevant Courses: Graduate Level

Advanced VLSI Design, VLSI Design, Advanced Digital Logic, Analog Integrated Circuits, Testing and Testable Design,

Computer Architecture, Power Management ICs

Technical Skills

Programming Languages: C, JAVA(J2EE), Verilog, Perl, VHDL, Spice, MatLAB, PL/SQL, XML

EDA Tools: Cadence Virtuoso, Encounter, Tetra-MAX, Design Vision, Prime

Time, Liberty NCX

Software: Cadence, Pspice, LT Spice, Hspice, Model SIM, Simple Scalar

Laboratory Equipment: Oscilloscope, Spectrum Analyzer, Logic Analyzer

Operating Systems: Windows 7/XP, Sun Solaris, Linux

Projects

SRAM Memory Design - ( AVLSI Design )

- Custom Design and Layout, post layout analysis of 768 bit SRAM using IBM 90nm Technology

- Identified the best Read and Write Times, with design optimized for low power dissipation, fast access

times, minimal area and only two metal layers

- Post Layout analysis was performed in Hspice along with DRC and LVS evaluations

- Developed a standard library for automated layout and the results both custom and semi-custom design

were compared

Quad CORE ALU design - ( VLSI Design)

- Design of Quad core ALU, Layout design of basic gates with some special gates and D flip flop, minimization

of gate delays with optimum energy delay product

- Simulation using HSPICE and comparison with schematic, ncx library generation and characterization,

Automatic placing and routing using Encounter tool, DRC and LVS check on the entire chip, Primetime

analysis, and Simulation of the chip using HSPICE

• Advanced Digital Logic

Design of basic cell library

- Design of basic cells like NAND, NOR, OA221, DFF using 130 nm, and generation of models using

HSPICE. Using this library simulating various types of registers, RAM, PLA, counters, LFSRS.

Testing and Testable Design

- Using Synopsys tools like design vision and tetramax to find faults in designed circuits, comparing

this to the hand calculated values of faults patterns, Fault simulation and Pattern Generation.

- Design of s27 circuit. Insertion of scan flip flops, design of built in self-test circuits for these, Boundary

scan flip-flops design. Reporting patterns, comparison of patterns, Signature generation, storing and

analysis. Reporting area, power, delay for all the above circuits.

Testing Projects - (Digital System Testing)

- Various combinational and sequential circuits were synthesized fro m their behavioral descriptions and

synthesized designs were further used for generating ATPGs for various stuck at faults using Tetramax

- Sequential designs were synthesized and the critical paths were extracted from prime time which was

then used to generate Test Patterns for Path Delay faults in Tetra-Max

- A 4-bit comparator was made BIST testable by adding an 8-bit External-XOR LFSR, as pseudo random

pattern generator and 4-bit MISR as signature compressor

- A 4-bit counter up/down counter was designed using D flip-flops. Here the normal flip-flops were

replaced with scan Flip-flops to build one scan chain

Cache Design Optimization for Alpha Processor - (Computer Architecture )

- L1 and L2 level cache designs were optimized for obtaining a reasonable reduction in CPI for various

SPEC benchmarks

- A cost function relating the various parameters of cache was formulated w hich was later optimized for

lower CPI and cost and real estate area

- The CPI Cost product was compared with various benchm arks to obtain most optimum configuration

- Building of cross compiler for C code which needs to be converted into arm target code

- Installation and usage of virtual box, and implementation of Tomasulo simulator using FREEBSD

Five Stage MIPS processor implementation - (Computer Architecture )

- A Verilog based implementation consisting of all the basic building blocks, ALU, single level cache, 16 bit

Data registers, supporting eight Instructions

- Implementation of Tomasulo algorithm in tcl coding, and design a Tomasulo simulator

Design of a Fast-Settling, High-Gain Operational-Amplifier - (Analog Circuit Design)

- Implemented a two stage differential input and single ended output amplifier using the TSMC CMOS

0.35um technologies with minimal Power Dissipation

Areas of Interest: Integrated Circuit Design, Circuit Simulations, RTL Logic Implementation, CAD Algorithm

Implementations, Low Power Design, ASIC Design, Timing Closure, Library Characterization, DRAM, ZRAM, TRAM

Design

Research interest: DRAM Optimization, TRAM and ZRAM Design, Transistor less DRAM design, SSDs

Availability: Spring and summer 2014

Visa Status: F-1

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