Divya Desiraju

***E ***N Apt * Logan, UT ***** 435-***-****

acc634@r.postjobfree.com

EDUCATION:

Utah State University (Logan, UT, USA) Dec

2013

GPA:

Master of Science in Electrical and computer engineering

3.41/4

Jawaharlal Nehru Technological University (Hyderabad, India) May

2011

Bachelor of Technology in Electronics and Communication Engineering

GPA: 4/4

AWARDS AND ACHIEVMENTS:

• Awarded with Research Assistantship and Graduate Tuition benefit by U tah

S tate University

SKILLS:

Programming Languages: C, C++, Java, PERL, Python, Javascript, CSS, HTML,

ASP.NET, JQuery, SQL

Software Tools: CADENCE, HSPICE, MATLAB, Synopsys Design compilers, Soc

Encounter, Synopsys Prime Time (Static timing analysis tool), Modelsim, Visual Studio

Operating Systems: Windows, LINUX.

WORK EXPERIENCE:

Graduate Research Assistant, Utah State University, Logan, UT May 2012

August 2013

• Developing an algorithm for minimizing the disruption of traffic flow of

automated vehicles during lane changes and implement it using PERL (Real

Time Systems)

Graduate Teaching Assistant, Utah State University, Logan, UT August 2011

May 2012

• Worked as a grader for Digital Circuits ( August 2011 December 2011)

• Worked as a grader for Microcomputer Hardware and Software( Jan 2012 May

2012)

ACADEMIC PROJECTS:

Hostage rescue game using Java:

• SCOPE: the player pushes boxes or crates around in a warehouse, trying to

get them to storage locations

• SKILL SET: Java programming language is used to develop the game

Simulated Annealing algorithm for slicing floor plan using C++:

• SCOPE: First an initial solution (polish Expression) is selected. Then a

controlled walk through the search space is performed until no sizeable

improvement is made or we run out of time

• SKILL SET: C++ language is used to implement the algorithm

Student feedback system:

• SCOPE: World wide web based course feedback system serving both

students and teachers is developed

• SKILL SET: ASP.NET, HTML, CSS and JavaScript are used for developing

the project

Floating point 32 bit ALU (IEEE Standards 754) using VERILOG HDL:

• SCOPE: Designed a floating point 32 bit arithmetic unit including trigonometric

and logarithmic functions developed using cordic algorithms

• SKILL SET: VERILOG HDL for designing floating point unit, SYNOPSYS

DESIGN COMPILER is used in order to synthesize the module; Soc

ENCOUNTER is used for placement and routing of the module obtained

Minimizing the disruption of traffic flow of automated vehicles during lane

changes:

• SCOPE: Developing an algorithm for vehicle grouping and scheduling in

VANETS in order to optimize the total number of lane changes in a particular

given time

• SKILL SET: PERL is used to implement the algorithm. Submitted the above

mentioned project to IEEE

Effect of Diameter Variation in Carbon Nanotube FETs:

• SCOPE: Simulated a half adder circuit with CNTFET having different

dimensions

• SKILL SET: HSPICE is used to simulate the half adder circuit and 32nm

technology is used

High Performance Dynamic Memory Controller:

• SCOPE: High performance dynamic memory controller is designed to drive 32

bit DDR SDRAM memory

• SKILL SET: VERILOG HDL is used for the design and testing of the system

Characterization of standard cells using Current Source Modelling:

• SCOPE: Designed a standard cell library and characterized the cells using

Current Source Modelling

• SKILL SET: HSPICE is used for simulation of the standard cell library

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