[pic] Gulshan Malik, House No *** Sec ** D Near Water Tank,

Faridabad (Haryana) India.

[pic] 991*******, 975-***-****

[pic] acb8fz@r.postjobfree.com

Anubha Kushwah

Objective To utilize my professional skills & abilities in best

possible way and take the organization to the acme of

success.

Education YMCA, Faridabad, India - M (Tech.) - July 2011 - June

2013

69.58%

Major: Electronics & Instrumentation, Control

Engineering, Digital Circuit Systems

M(Tech.) Dissertation : Wavelet Threshold for Image

De-noising By Modified Chaos Particle Swarm

Optimization

ITM, Gwalior, India - B (Engineering) - June 2005 -

May 2009

77.81%

Major: Electronics & Instrumentation

BE Major Project: Noise Reduction from an ECG Signal

Carmel Convent School, Gwalior, India - 12 Std. - May

2005

68.4%

Major: Pre Engineering

Carmel Convent School, Gwalior, India- 10 Std. - May

2003

74%.

Certifications VLSI Front End Design - September 2013 - February 2014

CETPA InfoTech Private Ltd, Noida, India.

MATLAB - September 2013 - February 2014

CETPA InfoTech Private Ltd, Noida, India.

Projects Wallace Tree Multiplier

Implementation of 4-bit WTM using VHDL and its

hardware implementation on FPGA Spartan-3E

Booth Multiplier

Implementation of 4-bit Booth Multiplier using VHDL

and its hardware implementation on FPGA Spartan-3E

8-Bit UART

Implementation of 8 bit uart reciever and transmitter

using Verilog

Error Correction & Detection

Implementation of 8 bit orthogonal code for error

correction and detection using VHDL

Image Edge Detection

Implementation of edge detection algorithm using HDL

coder in MATLAB

Workshops National Level Workshop on Digital System & VLSI

Design

7 - 9 March 2008.

ITM Gwalior

Summer/ Industrial Training from Gas Authority of

India Limited

18 June 2008 - 2nd August 2008

New Delhi.

Skill Set VLSI Domain Skill Matlab

Hardware Descriptor Matlab Basics

Language Image Processing Toolbox

VHDL Control Toolbox

Verilog HDL Coder

Hardware Verification HDL Verifier

Language Microsoft Office

System Verilog MS Word

Hardware Kits MS Power Point

FPGA Spartan-3E XC3S250E MS Excel

CPLD - XC9572

EDA Tools

Modelsim

Questasim

Xlinx ISE

Languages English Hindi

Personal Information Date of Birth : May 7, 1987

Nationality : Indian

Marital Status : Single

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