CURRICULUM VITAE

ROBIN S JOHN

N**, Ward N*, Police Training School

Pachmarhi, Madhya Pradesh- 461881

E-mail: acb850@r.postjobfree.com

Phone No: +91-814*******

CAREER OBJECTIVE

CAREER

Looking for opportunities wherein I can utilize my pensive and competent technical skills to contribute

positively to the success of the organization.

EDUCATIONAL QUALIFICATIONS

Degree Institution Year Percentage

P.G Diploma CDAC, ATC - P ursuing

M umbai

B. Tech ECE Lovely Professional 20 78.66%

U niversity, Phagwara 13

HSC Kendriya Vidyalaya, 20 77.66%

Pachmarhi 08

SSC Kendriya Vidyalaya, 20 73.66%

Pachmarhi 06

TECHNICAL SKILLS:

TECHNICAL

: KEIL, Eclipse

Tools

: MATLAB

N umerical Analysis Tool

EDA Simulation Tools : ISIM, QuestaSim, ModelSim, NCSim

: XST, Leonardo Spectrum

Synthesis Tools

: Simulink, SCADA, Proteus, PSpice

G raphical programming Tools

: System Generator

DSP Systems Design Tool

: Xilinx

FPGA’s & CPLD

LANGUAGES:

LANGUAGES

Programming Languages : C, C++, Assembly, Ladder, and Perl

Hardware Languages : VHDL, Verilog

Verification Language : System Verilog

TRAINING:

TRAINING:

: BRICS Pvt. Ltd, I.I.T Kanpur

Organization

: June 14- July 18, 2011

Duration

: Worked on Embedded System and its Application and has

Description

made various projects Using A TMEGA16 (AVR)

m icrocontrollers.

: Sofcon Pvt Ltd, Bhopal

Organization

Duration : June 1-June 30, 2012

Description : Learned about the use of PLC and SCADA to control the processes

in the Industry

PROJECTS UNDERTAKEN

PROJECTS

Project : Design and verification of AMBA APB Bus

Objective : Design a bus for low-power peripherals.

Description : Designing APB bus using Verilog and create Verification

environment using System Verilog.

Project : Design and implementation of UART Using VHDL

Project

Objective : Study of Serial UART

Description : Design coding, Simulation, Logic synthesis and implemented will be

done using ModelSim -Altera6.5b

Project : Designed General Purpose 16-bit Microprocessor using Verilog.

Objective : To develop a software simulation of microprocessor.

Description : Designing of sub module like ALU, shift register, program counter,

register array, instruction decoder, control unit and integration of sub

module resulting in a functional microprocessor using Verilog on

Xilinx ISE 12.3.

AWARDS AND HONOURS:

U niversity Academic Honors 2009-10

Won First position in the R elay Rac e competition

Won Best W icket keeper Award

LANGUAGES KNOWN:

E nglish, Hindi, Malayalam

HOBBIES:

Listening music, Hiking, Camping

PERSONAL DETAILS:

Father’s name : Mr. Shaji John

Mother’s name : M rs. Sheeja John

Date of bir th : 08-07-1989

Gender : Male

DATE: ROBIN S JOHN

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