Balakrishna Reddibathina
Email : acb64l@r.postjobfree.com Contact No: +91-955*******
Objective
Seeking a challenging position in an organization, that offers professional growth and
provides a platform for exposing my skills and abilities.
Obtain a position as a team player in a people oriented organization where I can maximize my
project experience in a challenging environment to achieve the corporate goals.
Technical Skills
Hands on HDL Verilog.
Hands on HVL System Verilog.
Good knowledge of C.
Basic knowledge of UVM Methodology.
Hands on verification Experience with slow peripherals I2C, SPI and UART using
AXI VIP.
Exposure to protocols: AMBA-AXI/APB.
Knowledge of working with Modelsim and VCS simulators.
Professional Experience
Working as Project Intern in Mindspeed technologies from May 2013 to Dec 2013.
Educational Qualification
Bachelor’s Degree in Electronics and Communication Engineering, 2010 from
Narayana Engineering College, Nellore, Andhra Pradesh with 74.89%
Work Experience
Mindspeed Technologies India Pvt Ltd
Team : IDC
Project Title T3400 SoC verification
Duration 5 months
Description Transcede3400 is a new SoC for smallcell application with 4G/LTE
Responsibilities
VERIFICATION OF A PERIPHERAL SUBSYSTEM BLOCK USING AXI VIP
• Subsystem peripheral block contains the slow peripherals like I2C, SPI and UART
• Developed Test plan Document and Test Cases
• Create the Environment and tested with the features of all the peripherals in Both
VCS and QUESTA Modelsim.
• Create the tests in C language and tested unit level with our environment
MIGRATION FROM VCS TO MENTOR VIP:
• Being a part of tool migration responsible for migrating XP_Cluster from VCS VIP to
Mentor VIP.
• Got Good Knowledge on Usage of VIP and connecting it to the verification
Environment.
Project Title Training
Duration 3 months
Description As a trainee engineer
Responsibilities
AMBA-APB :
• Developed RTL for APB slave for which APB bridge is a master.
• Developed complete verification environment from scratch in system verilog which
includes BFM, monitor and score board.
• Generated various test cases to verify the DUT for various scenarios.
Synchronous FIFO:
• Developed RTL for Synchronous FIFO.
• Developed complete verification environment for a FIFO which includes BFM,
monitor and scoreboard.
• Generated various test cases for different scenarios.
Declaration
I hereby declare that the information furnished above is true to the best of my Knowledge.
Date
Place: Hyderabad (R.Balakrishna)