A. PARIKSHITH

acb612@r.postjobfree.com 903*******

OBJECTIVE:

Seeking an opportunity in VLSI industry with RTL Designer as

experience having design and verification knowledge for the improvement of

the company through continual experience.

WORK SUMMARY:

1 year 2month experience as RTL Design Engineer

Strong knowledge in Digital Designing

Good Knowledge in VHDL, Verilog, System Verilog languages.

Familiar with FPGA based design and Verification, Xilinx and Questasim

tools.

Bus protocol: UART, AHB, OCP.

Trained in LUCID VLSI on System Verilog Verification with practice session

on Router

WORK EXPERIENCE:

Working as Design Engineer in QWERTY Technologies Pvt. Ltd., Hyderabad

since August 2013.

Worked as Design Engineer in Simpli5NG Semiconductors Pvt. Ltd., Hyderabad

since August 2012 to July 2013.

Technical Skills:

. Programming Languages: C

. Hardware Languages: VHDL, Verilog, System Verilog

. Hardware Tools: Xilinx, Questasim, cygwin.

. Operating System: Windows

Projects handled:

Company: QWERTY TECHNOLOGIES

Designation: Design Engineer

Duration: Since August 2013

Project: Design of On-chip bus with OCP Interface

Tools: Modelsim

Language: Verilog

Description: the Open Core Protocol (OCP) focus on the design of the

internal bus architecture. We develop an efficient bus architecture to

support most advanced bus functionality defined in OCP burst

transactions.We first model and design the on-chip bus with transaction

level modeling for the consideration of design flexibility and fast

simulation speed. We then implement the RTL models of the bus for synthesis

and gate-level simulation.

Roles & Responsibilities:

Understanding the specifications from the scratch

Implementing the RTL based Design in Modelsim tool.

Simulate and synthesize the design for Netlist generation

Verifying the design on the FPGA with the Xilinx tool

Additional endeavors: Conducted VLSI awareness workshop at JNTU for BE

students

Company: Simpli5NG Semiconductors Pvt. Ltd., Hyderabad

Designation: Design Engineer

Duration: October 2012- July 2013

Project: Computational sharing programmable FIR Filter for Low-power and

High-performance Applications.

Tools: Xilinx, Questasim.

Description: This is based on a computation sharing multiplier (CSHM)

which specifically targets computation re-use in vector-scalar products and

can be effectively used in the low complexity programmable FIR filter

design.

Duration: January - March 2013

Project: Distributed Arithmetic for FIR Filter Implemented on FPGA.

Tools: Questasim, Xilinx.

Description: A new design and implementation of FIR filters using

Distributed Arithmetic is provided in this project against the traditional

method, aiming to improve the system speed and reduction of hardware

resources

Duration: April - june 2013

Academics:

. B.Tech (Electronics & Communication) at Aurora's Scientific &

Technological Research Academy from JNTU-H, with 60 % aggregate in

April 2011

. Intermediate from Sri Chaitanaya Junior kalasala with 55% specialized

in Mathematics, physics & Chemistry -2005

. SSC from Sri Vani Vidyaniketan High school with 63 % - 2003

Achievements :

. Participated in National level 'standing coco' competition held at

Lucknow in 2003

. Participated in many sports at college level

Academic projects :

Main project: Implementation of Convolution code using Verilog.

Tools: Modelsim.

Description: used in image processing scaling, sampling, rotation to get

clear image.

Technologies involved: used in digital image processing.

Mini project: design and implementation of encoder for (15,k) binary BCH

code.

Tools used: Xilinx.

Description: used in communication system for error correction and error

detection.

Technologies involved: communication system.

I hereby declare that all the information provided above is true to the

best of my knowledge and belief

(A. Parikshith)

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