KIRAN KUMAR APPALA
E-mail: acb26l@r.postjobfree.com, Mobile: +91 -872-***-****
Sri Venkata Sai P.G,Hemanth Nagar,Marthahalli,Bangalore, KA-560037
PROFILE:
Currently working in LSI India Research and Development Pvt Ltd (Masamb Electronics Systems Pvt Ltd)
w ith total 1.6 years of experience in VLSI domain at LSI (6months) as design engineer and ST. Microelectronics
(1 year) as intern. Looking for c hallenging opportunities in VLSI domain.
ACADEMIC RECORD:
Year of
Class/Course Name of Institute B oard/University M arks%
Passing
Manipal Centre for
Master of Science 8.0
Information Manipal University 2013
( VLSI-CAD) (C.G.P .A)
Science,Manipal
Bachelor of Mother Theresa
technology Institute of Science Jawaharlal Nehru
2011 70
(Electronics & and Technology Technological University
Communication) College, Sathupally
Nettur Technical
Diploma Nettur Technical Training
Training Foundation 2006 75
(Mechatronics) Foundation
Coimbatore
Bhashyam
Secondary School Board of Secondary
P ublic school 2003 74.3
Certificate Education
Guntur.
I NDUSTRIAL EXPERI ENCE:
Organization : LSI India Research and Development Pvt Ltd.
Role : Quality Assurance in Memory Models .
Employer : Masamb Electronics Systems Pvt Ltd.
(August,2013 – Till now).
Project description:
Worked on 28nm and 16nm Memory Compilers (UHS, RF, and HD).
Responsibilities:
Involved in
Feasibility analysis of the Memory Cut requests.
Verifying all the views of memory compilers.
Support QA scripts for automation
Verifying the hspice netlist using Verilog model.
Analyzing the test patterns and inserting the missing patterns for given feature set.
Tools used:
NCSIM, MODELSIM, VCS,Hspice.
Organization : ST Microelectronics private Ltd.
Role : Memory Model Development in 28nm and 20nm Techno Nodes.
(June 2012 – July 2013).
Project description:
Worked on SRAMs such as T ernary Content Addressable Memory (TCAM), Single Port High Speed (SPHD)
Single Port Registers (SPREG) and Dual Port Registers ( DPREG).
Responsibilities:
Involved in
Understanding the Memory Specifications.
Feasibility analysis of the Memory Cut requests.
Verifying and resolving the bugs in the memory model.
Development of DFT Model in Verilog.
Verifying the Verilog Models using eVC (Specimen verification environment).
Generating Test Pattern Using Tetramax/ Fast Scan and Verifying the DFT model using NCSIM
functional Simulation.
Tools used:
NCSIM, MODELSIM, VCS, eVC ( e -language verification component), Tetramax, Fastscan.
ACADEMIC PROJECTS:
M.S Mini Projects:
Title: High Performance Full Adder Cell: A Comparative Analysis
Project Description : Implemted full adder in 3 architectures i.e., 16T, 10T, 8T and their performance
c omparison and analysis . Circuits are implemented in TSMC 90nm and 180nm technology .
Title: I nterfacing the Monitor with FPGA
Project description: Displaying the Message on the monitor by using Xilinx Vertex -5 board.
TECHNICAL SKILLS:
o ASIC Front End
RTL Design
DFT
Functional Simulation and Debug
T iming Analysis
o ASIC Back End
Layout Projects
o FPGA Prototyping
EDA TOOLS: Xilinx ISE simulator, Cadence Ncsim, Synopsys VCS, Mentor-Fast scan, Synopsys T etramax,
eVC.
HDLs : Verilog and VHDL
OPERATI NG SYSTEMS : Windows 8/7,Linux .
SCRIPTING : Perl and Shell
BEHAVIORAL LANGUAGES : C
PERSONAL PROFILE:
Name : Kiran Kumar. A
Father’s Name : Chinna Sankara Rao. A
Sex : Male
Marital Status : Single
Date of Birth : 18-07-1987
Nationality : Indian
Languages known : English, Telugu, Hindi and Tamil.
DECLARATION:
I declare that the above mentioned particulars are true to the best of my knowledge and belief.
PLACE:
D ATE:
(KIRAN KUMAR.A)