Vishnu Kaushik Reddy Moole

** ********* ****, *-****: acaskw@r.postjobfree.com

Door No. 2, Marlborough, MA-01752. Mobile

No.: 480-***-****

OBJECTIVE

Self-motivated student seeking an innovative and challenging full time

position in the field of Electrical Engineering.

EDUCATION

. BS(Electronics Communication Engineering), Jawaharlal Nehru

Technological University GPA- 3.8 May 2012

. MS(Electrical Engineering), Arizona State University CGPA-3.8

May 2014.

. Courses

*Analog Integrated Circuits *Digital Systems

and Circuits *Semiconductor and Device Theory

*Advanced Hardware and System Design *VLSI Design

*Computer Architecture

TECHNICAL SKILL-SET

Softwares/IDEs : Pspice, Cadence, Virtuoso, Caliber, Hspice, MS

Office, Synergy, ModelSim/QuestaSim, Xilinx, Altera.

Programming languages : C, C++, Java, VHDL, Verilog, System Verilog,

MATLAB, Perl, TCL.

Operating System : Windows 95/98/2000/XP/7/8, Vista, Linux, MAC,

UNIX.

INTERNSHIP

Intel at Hudson, MA

(July'13-Jan'14)

I am working as a Graduate Technical Intern in a FPGA design/Verification

team. My work involves writing Perl scripts for data parsing, creating new

test cases written in OVM, testing and debugging the tests according to the

architecture provided. I modified the OVM sequences and also add new

sequences and functions to the library.

ACADEMIC PROJECTS

Error detection and correction using Hamming code (RTL Compiler, ELC,

ENCOUNTER, Verilog) (Jan'13 - Feb'13)

. A generic synthesizable code for hamming encoder and decoder was

written in Verilog. A TCL file was written which consists of the

Design specifications. Timing analysis was done(setup/hold timings).

. This file was sourced in a RTL complier and the code was synthesized.

Encounter tool was used to layout and ots floor plan, place and route.

Generated the clock trees connectivity errors. Passed the DRC and LVS.

Design of standard cell libraries (Technology: 45nm PDK)

Criteria- Minimum area

(Jan '13- Feb'13)

. The standard gates like XOR, XNOR, NAND,NOR with 4 inputs have been

designed and layed out using industry standards for 3 different Vt

layers.

. The simulations are run to find out TpLH, TpHL, Vm, Noise margin for

different process corners FF, SS and NOM.

. The driving capability of the circuit is tested using an inverter

which is 4 times the size of the gate and the rise and fall times are

recorded. Generated Abstract(.lef) files, obtained the simulation

results from layout using ELC.

Design of an 8-bit Even parity generator (Technology: TSMC 0.25 m)

Criteria- Minimum Energy Delay Product(input sequence - 5 28 222 7 19) and

layout area (Aug'12 - Dec'12)

. An 8 bit even parity Generator is designed using 7 2 bit XOR gates

which in turn are built using Transmission gates to optimize the

energy delay Product.

. The input and output registers are TSPC latches. The layout of the

circuit was done suing industrial standards.

. The energy delay product calculated for the input sequence is 2.51

ns*pJ. The obtained layout area is 782( m)

Verification of a 4 Port Switch (HVL: System Verilog)

(Jan '13- Feb'13)

. The inputs are written using a single driver but the output has 4

ports with addresses assigned. The input is a random data frame with

variable data length.

. The interfaces for the switches, memory modules and the output ports

were written. Constraint based random verification methodology was

used to verify the design.

Design of Asynchronous FIFO (HDL: Verilog, HVL: System Verilog)

(Jan '13- Feb'13)

. The high speed asynchronous FIFO is designed using dual port RAMs

addressed by Gray counters.

. The critical paths for cases like stack and empty are found and

Asynchronous comparator is used for detecting full and empty status.

Synchronization of FIFO pointers into opposite clocks is accomplished

using gray code pointers.

Design of a Audio Amplifier with active load. (Technology: TSMC 0.3 m)

(Aug'12 - Dec'12)

Criteria - Voltage swing of 0.5V Gain of 40dB

. The amplifier is designed by cascading single ended differential

amplifier and a PMOS source follower. A voltage divider is used as a

feedback element. The transistor sizes are increased to meet the gain

and the output criteria. The DC biasing is given to the differential

amplifier using a constant current source of 20 A

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