Paramjit Singh

Ph. (***) ***- ****

**** ******* *** **.

acasf3@r.postjobfree.com

Lorton, VA 22079

OBJECTIVE

Challenging position in photolithography/etch area that utilizes my sustaining/development experience in

semiconductor industry, project management, staff recruitment/retention, collaboration/ presentation skills and helps

influence organizational growth and bottom-line profitability.

PROFESSIONAL ACHIEVEMENTS

Involved in startup and ramp a fab from 2.5k to 16k wspw while enabling 3 technologies with benchmark

world class yields, currently running sub 30 nm processes.

Set up robust business processes for technology transfer from R&D to manufacturing sites and enabled four

successful technology transfers from startup to full ramp with >90% yield.

Lead various cross functional area teams that helped organization meet output and yield goals and help me

gain knowledge about etch, CVD, CMP processes.

Established a successful photo process team by external hiring, mentorship program for internal candidates

and setting up KPI’s/business processes by collaborating with various internal and external stake holders.

Improved CD and overlay CpK of various photo processes by understanding sources of variation by

effective data mining, tools/materials contribution and implementing process improvements, run to run

controller or tool dedication or tool improvements.

Lead teams involved in defect reduction across various modules and implemented fixes to achieve

benchmark yields of >90% for 2x nm nodes.

Lead cost reduction projects for example photo consumables cost reduction by 40%, elimination of non-

value added steps from the traveler by effective collaboration with various stakeholders.

Enabled latest equipment from ASML (1450, 1950H/NXT), TEL Tracks (Lithius Pro/ProV), AMAT CD

SEM’s (4i) by partnership with equipment/application owners and other stakeholders.

Lead cross site team which helped test wafer cost by 70% resulting in ~$12 million/year savings.

Patented device isolation scheme for BiCMOS process that lead to robust yields.

EXPERIENCE

MICRON TECHNOLOGY, VIRGINIA (Sept. 2004 to Present)

Photo Process Lead NAND Technology (March 2010 to Present)

Leading a group of seven photo engineers involved in reticle quality/management, sustaining sub 30nm

NAND technologies and development of NOR technology and introduction of new parts on current technology

nodes. Key accomplishments include setting up business processes by aligning with key customers,

establishing KPI’s for safety/quality/output and setting up a successful team that values the importance of

adhering to the agreed upon business processes with each team member holding themselves accountable to the

agreed upon project timelines and proactively escalating to management any roadblocks that can cause

negative project floats.

Team’s key accomplishments include;

Cross cluster quals for better CAU due to changing business needs for example qualification of

immersion levels on 193 dry tools, implant levels between i-line/DUV.

Enabled robust processes by working with OPC group or process improvements resulting in 50%

improvements in DOF or CD budget.

Implemented cost reduction projects including resist volume reduction, resist consolidation and FIRM

reduction that resulted in 15% cost reduction.

Partnered with immersion scanner owner, dry etch, CMP and PI for edge yield improvement up to 82%

by implementation of proactive chuck cleans based on inline scanner data and using scanner data to

flag incoming issues.

Enabled new polyimide material and worked with sister sites to enable clustered polyimide process.

Collaborated with sister site track materials owner, RDA, PI/PQA team across the sister sites to plan

resist batch qual strategies to mitigate material related excursions.

Improved overlay performance to industry benchmark levels by implementation of chuck dedication,

latest overlay enhancement schemes (CPE, higher order grid/field etc.), chuck dedication and working

towards implementation of baseliner across all critical tools.

Reduced reticle related excursions by proactive flagging, sending reticles for cleans and successfully

aligned with Fab Leadership team on need for reticle stocker in a high volume manufacturing fab.

Mentored shift engineering team to take over legacy technologies.

Senior Engineer Photolithography (Sept 2004 to Mar 2010)

As a key member of the photo team supported fab’s ramp from 2.5k wafers per week to 16k in 3 years by timely

release of tools based on key inline data and tool parameters. Key accomplishments include

Successful transfer of 3 technologies from R&D to manufacturing and achieving 70-80% yields within 9

months and mature benchmark yields within 1 to 1.5 yrs.

Enabled 193 dry and 193 immersion processes on 3x nm nodes and fully loaded immersion tools in 3-4

weeks.

Understanding of lens heating on 193d and implementing fixes/restrictions to mitigate the impact of

lens heating on yield or CpK for critical CD/overlay charts.

Implemented photo process changes to mitigate the impact of amine contamination due to incoming

substrate or photo processes/materials resulting in Cpk improvements by 50%.

Enabled fast i-line resists thus preventing $20 million of capital costs.

Collaborated with stakeholders on ROI on edge field reduction on scanner constrained parts (even with

some yield loss) resulting in 15 wafers per hour scanner throughput improvement and leading cross-

functional team for edge yield recovery with reduced shot count.

Partnered with track team on process improvements resulted in for 15-20% improvement in baseline

defectivity.

INTEL TECHNOLOGY, CALIFORNIA (Aug 1997 to Aug 2004)

Photo Group Lead (Oct 2001 to Aug 2004)

Lead group of 12 shift engineers/technicians involved in sustaining photo/etch area in a sub 100nm fab,

helping process team expediting experiments in the fab and tool releases. Key accomplishments of the team

was increasing CpK of gate level ADI/ACI CD from 1 to 1.66, challenging process team to reduce noise on the

floor by having rework related goals.

Fab Support Manager (Jan 1999 to Oct 2001)

Lead a group of 40 engineers, technicians, production supervisors and MT’s in fab support group that included

wafer handling tools, parts clean and Silicon starts. Main accomplishments for the group were;

Reducing tool down related to TW’s quality/availability by 50%

Zero rejects due to parts clean issues

50% reduction in wafer breaks due to wafer handling issues.

Silicon Engineer (Aug 1997 to Jan 1999)

As a test wafer owner at a development/pilot line proposed project to reduce the test wafer costs by 80% by

effective internal reuse and regeneration of test wafers. Once approved, partnered with sister site test wafer

engineers, cross site process/module owner teams to implement the project that resulted in about $12

million/yr savings across the whole factory network.

NATIONAL SEMICONDUCTOR, CALIFORNIA (Mar 1993 to Aug 1997)

Dry Etch Engineer

Owned isolation, contact/via etch and SOG etch back processes in a six inch pilot fab involved in

BiCMOS/CMOS processes at sub 1 micron node. Main accomplishment included fixing chronic zero yield lots

related to the BVCEO issue. By partnering with device modeling engineer and photo engineer issue was

resolved by finding optimum focus for isolation at photo step. Also published couple of patents related to

modified SWAMI isolation.

INTEL TECHNOLOGY, CALIFORNIA (Sept 1991 to Mar 1993)

Process Technician

Worked as an off shift process technician in photo area, helping first shift team running experiments in a

0.5um fab running BiCMOS process. Key accomplishments include flagging a reg tool that was reporting

corrupt data due to particles in the film. Issue was escalated to tool owner and corrected with a software fix.

SEMICODUCTOR COMPLEX Ltd. INDIA (July 1985 to May 1990)

Process Owner (Photo/Dry Etch)

Participated a team involved in the startup of a 4 inch wafer fab in collaboration with AMI Gould, USA.

Successfully achieved 60% yield

EDUCATION AND CERIFICATIONS

MS in Physical Chemistry with Honors, Panjab University Chandigarh India

Certificate in Introduction to Semiconductor Device Physics, Indian Institute Of Technology (Kharagpur)

Six Sigma Black Belt (Micron Technology, VA)

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